From patchwork Fri Oct 13 17:21:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 115815 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp975238qgn; Fri, 13 Oct 2017 10:23:50 -0700 (PDT) X-Google-Smtp-Source: AOwi7QC25FXeQU6aZdZwPrKxcJErNYnY/4/20Y97sg2rGGyb3HMGUr5SfQGHEJPijtZAzxCBohqh X-Received: by 10.80.166.133 with SMTP id e5mr2990844edc.51.1507915430054; Fri, 13 Oct 2017 10:23:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507915430; cv=none; d=google.com; s=arc-20160816; b=NTJHaWE2xFN+8BYK642NbimC3oTnN3/zvkpGacNcT+IWsQvWAqI6RQrZY5wUKIsv/n bOO/lTgD54B4BfMogr0rlGkIKJ0r6Z07o1pxqo79H4IKOmNJk+AnBI4FUNDtpXpDcK9V nYqKEXXkNtnIidZiJDRpaJoBi7PRj5Yit0EbkbjHV08S5qgHsef9Z6fVvZKmCxdWpFcs STHbr0s4oC2VRXjy3j1Z8mj+G8KPWLbtzAJlDwTY+VQl2CmXh/GygfU8HMblRcwLWx/E ezThJRqXTzVFqtrQ8thKYB1UEV4dJ+0xgc0RR0ISxLOAbML9mVWbEsVkqyduud9iqvts x9Wg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:dkim-filter:arc-authentication-results; bh=O4hBC/+9jcHo2wC8SvZ6H/x5Glv05LpSf3ItkxMFPF0=; b=0xcfKgGDyPEhg6ioPX/kB6j5Usp3dZ1k+AEITv8wDdOMuOqVOTWgXyVjyQ3N1PygF1 6x84UN8M61vNvjD9NSAGAz6j90bTk/kqgW0ZdSMr+6Kb/Eo7DvbqAB9SCXqJJdcAxtDr LcUaNpXt/TsjSKn5x2caeR+ON8ry8KMal3fEg/TFM33pv7FZFkGooKDvWNjqQa7p6qww zpPWY186fyCzk1pcmBgg0eCUVpa7McLxcwYqWt7sDkjH7H7CsWsqZ+jRIlNDNN+eVCiO K6tiymBS03dquaUTXfcNVXQVJqW0GS0k8fi0biL0qnsdcRft2m1YHF7weVUr/3cjSuiR ARtQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=f128QxmW; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id a3si1140183edd.224.2017.10.13.10.23.49; Fri, 13 Oct 2017 10:23:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=f128QxmW; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id A29ABC22022; Fri, 13 Oct 2017 17:23:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B041EC2201F; Fri, 13 Oct 2017 17:23:03 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B44C9C21CEC; Fri, 13 Oct 2017 17:23:01 +0000 (UTC) Received: from conuserg-08.nifty.com (conuserg-08.nifty.com [210.131.2.75]) by lists.denx.de (Postfix) with ESMTPS id 6BB3DC21CEC for ; Fri, 13 Oct 2017 17:23:00 +0000 (UTC) Received: from grover.sesame (FL1-122-131-185-176.osk.mesh.ad.jp [122.131.185.176]) (authenticated) by conuserg-08.nifty.com with ESMTP id v9DHMXpi019395; Sat, 14 Oct 2017 02:22:34 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-08.nifty.com v9DHMXpi019395 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1507915355; bh=uVDw0Jk1T3if+ph7SScjkqk1F1g8c26AtWNoY+lfb3g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=f128QxmWDhaucTlYW9aXIPEo57m2vJSNg5cA1FJq11iJUC5fLEOMG9j+W+BmkNnjx jnTOVdV1bwRy5TxSl4Lij+8G7CDRbHU2mzUndNKYvS34Cj/a1Jmu1Vvbv6Um97K7Yq y5bVo4ZW3pB43jr6xkSCG8u+K4+6rKbcm3NFVBerKSXIDLY1QReyMbtnXprq+osTU5 jhxXcgFsFbfYgn4EvuCFlYyYCXIt4UUu7wHsijIp9V5P3nMdZGl2R5oWAzIIL0+V48 u8g4ktorpWphy1VVRG3XbcbvZIhvbd+xq7VqGJ78NCIsUGE0yU7tnrPG5A8uL0nLFD P5BEpPUPpSrbg== X-Nifty-SrcIP: [122.131.185.176] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Sat, 14 Oct 2017 02:21:19 +0900 Message-Id: <1507915279-25058-4-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507915279-25058-1-git-send-email-yamada.masahiro@socionext.com> References: <1507915279-25058-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 4/4] clk: uniphier: add NAND controller clock X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This allows the NAND driver to enable clock and get its clock rate. Signed-off-by: Masahiro Yamada --- drivers/clk/uniphier/clk-uniphier-sys.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c index f8cf6da..c852c78 100644 --- a/drivers/clk/uniphier/clk-uniphier-sys.c +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -7,10 +7,20 @@ #include "clk-uniphier.h" +/* Denali driver requires clk_x rate (clk: 50MHz, clk_x & ecc_clk: 200MHz) */ +#define UNIPHIER_LD4_SYS_CLK_NAND(_id) \ + UNIPHIER_CLK_RATE(128, 200000000), \ + UNIPHIER_CLK_GATE((_id), 128, 0x2104, 2) + +#define UNIPHIER_LD11_SYS_CLK_NAND(_id) \ + UNIPHIER_CLK_RATE(128, 200000000), \ + UNIPHIER_CLK_GATE((_id), 128, 0x210c, 0) + const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD4) || defined(CONFIG_ARCH_UNIPHIER_SLD8) ||\ defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) ||\ defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B) + UNIPHIER_LD4_SYS_CLK_NAND(2), UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10), /* stdmac */ UNIPHIER_CLK_GATE_SIMPLE(12, 0x2104, 6), /* gio (Pro4, Pro5) */ UNIPHIER_CLK_GATE_SIMPLE(14, 0x2104, 16), /* usb30 (Pro4, Pro5, PXs2) */ @@ -23,6 +33,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20) + UNIPHIER_LD11_SYS_CLK_NAND(2), UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8), /* stdmac */ UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */ UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 12), /* usb30-phy0 (LD20) */ @@ -33,6 +44,7 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = { #if defined(CONFIG_ARCH_UNIPHIER_PXS3) + UNIPHIER_LD11_SYS_CLK_NAND(2), UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4), /* usb30 (gio0) */ UNIPHIER_CLK_GATE_SIMPLE(13, 0x210c, 5), /* usb31-0 (gio1) */ UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 6), /* usb31-1 (gio1-1) */