From patchwork Tue Nov 21 17:38:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 119374 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp5569424qgn; Tue, 21 Nov 2017 09:42:28 -0800 (PST) X-Google-Smtp-Source: AGs4zMaWiKWqc8DHVjEKu+07uznqzQlRfh/PrmQ0QxDZFSMs14EwXelfdy3et2YGLQElnQiDP1ir X-Received: by 10.80.205.143 with SMTP id p15mr26050760edi.255.1511286145937; Tue, 21 Nov 2017 09:42:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1511286145; cv=none; d=google.com; s=arc-20160816; b=d6y9dB834/mKTZUyps1s1t6yc+JMOtP4FPIul9wcaa79cO5F3XTWjU4CsfUFE8BAmQ C+ev9PR/wWTyEAm1w76N/WbWUw49Y1IuHh66o6ghJb1BdSX5OTA+FSuBy9o06UQsfKGh MwoR0tK0Ps0LQt4jfvX7G/7v7Lms9p4S2RBj7izBcsZ7+Muu1+FMIvnoAIEeZutW0DsN ZtO9Nquwjl2homqANin3BFFkNGv8SbDgIsCMPBjmOl4rL34Q2F+hilOSudpEZJA/Oew3 OX2KP7xSS+zETM7hyQBfE2dxTp6h2a7YxsxvG88e+0K+2RExF49wEferg16YDWpQIDqG jRXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:dkim-filter:arc-authentication-results; bh=HwcU7wYo4H8yqiCfmXAJHyFceHliaP6kAUac08gXHGk=; b=yEct+18ZYncUqnLkyRiGD4oDCV/y+MHybb9YWrVKxVra8O/zfDQDHuJu6U4mBsXxov kITyBss1sIwrIqj0UEN8381r853nqZgBYqtNhiFjTRyzjUH5LBjfEx/5ylEjwZm08xSM 7QSt1ykA1GfA9r4O6rwWIa2UV870UNf29OVqAwpgo8Hh4EhyPITDA9yuxO/7EVG21o7Q WAA7XRzsKf8Sr61/LhZE59gFXXembm+4gDohMLUP1R7N1eaUQ5fqRtdm1/j9n0Cq0+c6 DyZWFupVG87wMvHMvtwTpq3yWo8Iy+M0p3kg2XdT1cHl+l4hJa54BpHCa/XjUqNVhIh9 g+gA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=CD5KBh6G; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id a16si909668edj.480.2017.11.21.09.42.25; Tue, 21 Nov 2017 09:42:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=CD5KBh6G; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 50890C21F71; Tue, 21 Nov 2017 17:41:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 90F47C21F76; Tue, 21 Nov 2017 17:39:21 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id CF8FDC21F69; Tue, 21 Nov 2017 17:39:08 +0000 (UTC) Received: from conuserg-07.nifty.com (conuserg-07.nifty.com [210.131.2.74]) by lists.denx.de (Postfix) with ESMTPS id CD35BC21EE4 for ; Tue, 21 Nov 2017 17:39:06 +0000 (UTC) Received: from grover.sesame (FL1-125-199-20-195.osk.mesh.ad.jp [125.199.20.195]) (authenticated) by conuserg-07.nifty.com with ESMTP id vALHcbu1001225; Wed, 22 Nov 2017 02:38:42 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com vALHcbu1001225 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1511285922; bh=s+7V6YFcpLKoouG+IOkS/tcYP/wGhsd9PphhFVZt+4U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CD5KBh6G0FKOtM3iPva8sAqTJfG5wHEP4w+zYnJECONi7cCbKLXOYtVF/Nc/M+RPd 3rvLEdKm0NgkOtsxgrzhxliElpzhoY8FsZoG+wSkInDV7iJ5msWCrfrDGdi2klLXE2 ZOwilkuKHmqSWLFxylDxF+nNe6Fb8UIWJWk3RYHN1w7EpaKbll7SsTc+SGFskel0Ir nueFIgAo9/bF8gV4IfsMQg87xHQTnyrCsKkyTBbQDQoP4PzcZUGw/lxXaiW0970sY8 q8yLVpU9Zpvp0oLOCFOOlRhs36ur1vnbHw6D4TBqx58pMprOO1kgEtSmiK/OZMtJZy 6nHAhPRm4WPgA== X-Nifty-SrcIP: [125.199.20.195] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Wed, 22 Nov 2017 02:38:21 +0900 Message-Id: <1511285912-12452-12-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1511285912-12452-1-git-send-email-yamada.masahiro@socionext.com> References: <1511285912-12452-1-git-send-email-yamada.masahiro@socionext.com> Cc: Scott Wood Subject: [U-Boot] [PATCH 11/22] mtd: nand: Add a few more timings to nand_sdr_timings X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Boris Brezillon Add the tR_max, tBERS_max, tPROG_max and tCCS_min timings to the nand_sdr_timings struct. Assign default/safe values for the statically defined timings, and extract them from the ONFI parameter table if the NAND is ONFI compliant. Signed-off-by: Boris Brezillon Tested-by: Marc Gonzalez [Linux commit: 204e7ecd47e26cc12d9e8e8a7e7a2eeb9573f0ba Fixup commit: 6d29231000bbe0fb9e4893a9c68151ffdd3b5469] Signed-off-by: Masahiro Yamada --- drivers/mtd/nand/nand_timings.c | 26 +++++++++++++++++++++++++- include/linux/mtd/nand.h | 8 ++++++++ 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/nand_timings.c b/drivers/mtd/nand/nand_timings.c index ba4f22f..9935557 100644 --- a/drivers/mtd/nand/nand_timings.c +++ b/drivers/mtd/nand/nand_timings.c @@ -17,6 +17,8 @@ static const struct nand_data_interface onfi_sdr_timings[] = { { .type = NAND_SDR_IFACE, .timings.sdr = { + .tCCS_min = 500000, + .tR_max = 200000000, .tADL_min = 400000, .tALH_min = 20000, .tALS_min = 50000, @@ -57,6 +59,8 @@ static const struct nand_data_interface onfi_sdr_timings[] = { { .type = NAND_SDR_IFACE, .timings.sdr = { + .tCCS_min = 500000, + .tR_max = 200000000, .tADL_min = 400000, .tALH_min = 10000, .tALS_min = 25000, @@ -97,6 +101,8 @@ static const struct nand_data_interface onfi_sdr_timings[] = { { .type = NAND_SDR_IFACE, .timings.sdr = { + .tCCS_min = 500000, + .tR_max = 200000000, .tADL_min = 400000, .tALH_min = 10000, .tALS_min = 15000, @@ -137,6 +143,8 @@ static const struct nand_data_interface onfi_sdr_timings[] = { { .type = NAND_SDR_IFACE, .timings.sdr = { + .tCCS_min = 500000, + .tR_max = 200000000, .tADL_min = 400000, .tALH_min = 5000, .tALS_min = 10000, @@ -177,6 +185,8 @@ static const struct nand_data_interface onfi_sdr_timings[] = { { .type = NAND_SDR_IFACE, .timings.sdr = { + .tCCS_min = 500000, + .tR_max = 200000000, .tADL_min = 400000, .tALH_min = 5000, .tALS_min = 10000, @@ -217,6 +227,8 @@ static const struct nand_data_interface onfi_sdr_timings[] = { { .type = NAND_SDR_IFACE, .timings.sdr = { + .tCCS_min = 500000, + .tR_max = 200000000, .tADL_min = 400000, .tALH_min = 5000, .tALS_min = 10000, @@ -289,10 +301,22 @@ int onfi_init_data_interface(struct nand_chip *chip, *iface = onfi_sdr_timings[timing_mode]; /* - * TODO: initialize timings that cannot be deduced from timing mode: + * Initialize timings that cannot be deduced from timing mode: * tR, tPROG, tCCS, ... * These information are part of the ONFI parameter page. */ + if (chip->onfi_version) { + struct nand_onfi_params *params = &chip->onfi_params; + struct nand_sdr_timings *timings = &iface->timings.sdr; + + /* microseconds -> picoseconds */ + timings->tPROG_max = 1000000ULL * le16_to_cpu(params->t_prog); + timings->tBERS_max = 1000000ULL * le16_to_cpu(params->t_bers); + timings->tR_max = 1000000ULL * le16_to_cpu(params->t_r); + + /* nanoseconds -> picoseconds */ + timings->tCCS_min = 1000UL * le16_to_cpu(params->t_ccs); + } return 0; } diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 8cff83b..8b76275 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -595,6 +595,10 @@ struct nand_buffers { * * All these timings are expressed in picoseconds. * + * @tBERS_max: Block erase time + * @tCCS_min: Change column setup time + * @tPROG_max: Page program time + * @tR_max: Page read time * @tALH_min: ALE hold time * @tADL_min: ALE to data loading time * @tALS_min: ALE setup time @@ -632,6 +636,10 @@ struct nand_buffers { * @tWW_min: WP# transition to WE# low */ struct nand_sdr_timings { + u64 tBERS_max; + u32 tCCS_min; + u64 tPROG_max; + u64 tR_max; u32 tALH_min; u32 tADL_min; u32 tALS_min;