From patchwork Tue Nov 21 17:38:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 119381 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp5573120qgn; Tue, 21 Nov 2017 09:46:07 -0800 (PST) X-Google-Smtp-Source: AGs4zMYUAzXea1NY/F0ey3TmoL5wWph7LswLS1w76Cy6HdXvUMQInF9HJqRVDPEV7sO0iu3HreIs X-Received: by 10.80.172.122 with SMTP id w55mr26042461edc.144.1511286367604; Tue, 21 Nov 2017 09:46:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1511286367; cv=none; d=google.com; s=arc-20160816; b=ogNMKw7jVeVD3Tl0yFLF1KtneS0j3Bsf37OOQa/YohefqluyUqrlRMuDr2ycnYkKo1 nvXRKMbzF1UsgKFA0pIUN6IcVKvkWdfO1eCzPZ2w2ZmU3/oafJEjuWUxj+bcTtkG61FB f8JbiugCMw8peW+XDprOwxFiyVb40c+YtUe4md7VhNxKjCVn7FdeP9F2PLSXqhLC/Ncq +wL671HE16MfdlmEGgdLxHO6UJQlJYOH0lT8gSC/zejBEamYwOPYP3bCL5hjXtf8+Pc+ YcmEUTbC8JVlwvtsy1E4jTKAm7VlmeizvL+6VPqh4stPPiB4p6+Hndae3orHQ4I/r7EJ 4qNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:dkim-filter:arc-authentication-results; bh=lZUPajJNt/sekdB35abHQpPB0ZHvw2TikGYzIHGnXls=; b=NT6waT37uDLdAhFgYZHJT77GGkC1gGHjmSmCNFaQOx5lEAIAaf8dArvD0Hqp74euIB fp5ADKO1TU92pLklplpaaTm7edOQzKALgoWzg+Xzvv0yDyPyb5NXuXee2AV56J+/D7YK D9xAar3wV26D1jOKnOx+KQ2xY4bH+bFfYgfB9X6WgWVzdd7fnKUzbddOWYFD+nO2GL2R wreUc4EFJF3kaxiGl5826osMzp6fyGhLEmXWWjzOQi3BUFOAQGvUSSUOFHlYWwvW7ohk qVHQGuGEtSHbvLpbDT/qicGfOFGmjx5mFQ/9QQzgmBQfNwa8d3TtjSZLufHQ/iLkWlm5 PvCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=tAvJhEgc; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id i17si3095836edg.395.2017.11.21.09.46.07; Tue, 21 Nov 2017 09:46:07 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=tAvJhEgc; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 213A3C21F31; Tue, 21 Nov 2017 17:43:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 66CF0C21F91; Tue, 21 Nov 2017 17:39:32 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 79B33C21F88; Tue, 21 Nov 2017 17:39:07 +0000 (UTC) Received: from conuserg-07.nifty.com (conuserg-07.nifty.com [210.131.2.74]) by lists.denx.de (Postfix) with ESMTPS id ED6E2C21F0F for ; Tue, 21 Nov 2017 17:39:03 +0000 (UTC) Received: from grover.sesame (FL1-125-199-20-195.osk.mesh.ad.jp [125.199.20.195]) (authenticated) by conuserg-07.nifty.com with ESMTP id vALHcbu8001225; Wed, 22 Nov 2017 02:38:45 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com vALHcbu8001225 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1511285925; bh=72ytamnGue2OKahVu94xkDaUguCIa2qd8G8mU2Bu4KQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tAvJhEgc0aNjpWv4xWaoguf7sPRzxMT+M1i/MY1kGgybuggTy5ZvMIPJROqZSE/zG pDvsRxIq87d53f7lfLk1cmMJ8y+cqjt6v2Fj01AXESCyKUvfUZnrwz28OXgfFx5HZp TUl6E56iyW2UNgAJNp66VUJFCHfMmjiulxZdWa8k8bGnj0D5Did+WAF4L9xy/xF9Ir lNHYEHj3qPwoXwcYKGx4s20mZGLW3Go8Mtx5yrFnrq0L/GFAKc7t6d1eLDSNwYZUkY /PynVkxK9jaDZ+hyhdfof46gVVkhm2SQSYoeVAYV1F4iPBwkBmxl0rB0blwk5tueeM 4IM5P9ixJVp6Q== X-Nifty-SrcIP: [125.199.20.195] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Wed, 22 Nov 2017 02:38:28 +0900 Message-Id: <1511285912-12452-19-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1511285912-12452-1-git-send-email-yamada.masahiro@socionext.com> References: <1511285912-12452-1-git-send-email-yamada.masahiro@socionext.com> Cc: Scott Wood Subject: [U-Boot] [PATCH 18/22] mtd: nand: Pass the CS line to ->setup_data_interface() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Boris Brezillon Some NAND controllers can assign different NAND timings to different CS lines. Pass the CS line information to ->setup_data_interface() so that the NAND controller driver knows which CS line is concerned by the setup_data_interface() request. Signed-off-by: Boris Brezillon [Linux commit: 104e442a67cfba4d0cc982384761befb917fb6a1] Signed-off-by: Masahiro Yamada --- drivers/mtd/nand/nand_base.c | 22 +++++++++++++--------- include/linux/mtd/nand.h | 12 ++++++++---- 2 files changed, 21 insertions(+), 13 deletions(-) diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index f3c515b..e490c84 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -904,12 +904,13 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) /** * nand_reset_data_interface - Reset data interface and timings * @chip: The NAND chip + * @chipnr: Internal die id * * Reset the Data interface and timings to ONFI mode 0. * * Returns 0 for success or negative error code otherwise. */ -static int nand_reset_data_interface(struct nand_chip *chip) +static int nand_reset_data_interface(struct nand_chip *chip, int chipnr) { struct mtd_info *mtd = nand_to_mtd(chip); const struct nand_data_interface *conf; @@ -933,7 +934,7 @@ static int nand_reset_data_interface(struct nand_chip *chip) */ conf = nand_get_default_data_interface(); - ret = chip->setup_data_interface(mtd, conf, false); + ret = chip->setup_data_interface(mtd, chipnr, conf); if (ret) pr_err("Failed to configure data interface to SDR timing mode 0\n"); @@ -943,6 +944,7 @@ static int nand_reset_data_interface(struct nand_chip *chip) /** * nand_setup_data_interface - Setup the best data interface and timings * @chip: The NAND chip + * @chipnr: Internal die id * * Find and configure the best data interface and NAND timings supported by * the chip and the driver. @@ -952,7 +954,7 @@ static int nand_reset_data_interface(struct nand_chip *chip) * * Returns 0 for success or negative error code otherwise. */ -static int nand_setup_data_interface(struct nand_chip *chip) +static int nand_setup_data_interface(struct nand_chip *chip, int chipnr) { struct mtd_info *mtd = nand_to_mtd(chip); int ret; @@ -976,7 +978,7 @@ static int nand_setup_data_interface(struct nand_chip *chip) goto err; } - ret = chip->setup_data_interface(mtd, chip->data_interface, false); + ret = chip->setup_data_interface(mtd, chipnr, chip->data_interface); err: return ret; } @@ -1027,8 +1029,10 @@ static int nand_init_data_interface(struct nand_chip *chip) if (ret) continue; - ret = chip->setup_data_interface(mtd, chip->data_interface, - true); + /* Pass -1 to only */ + ret = chip->setup_data_interface(mtd, + NAND_DATA_IFACE_CHECK_ONLY, + chip->data_interface); if (!ret) { chip->onfi_timing_mode_default = mode; break; @@ -1055,7 +1059,7 @@ int nand_reset(struct nand_chip *chip, int chipnr) struct mtd_info *mtd = nand_to_mtd(chip); int ret; - ret = nand_reset_data_interface(chip); + ret = nand_reset_data_interface(chip, chipnr); if (ret) return ret; @@ -1068,7 +1072,7 @@ int nand_reset(struct nand_chip *chip, int chipnr) chip->select_chip(mtd, -1); chip->select_chip(mtd, chipnr); - ret = nand_setup_data_interface(chip); + ret = nand_setup_data_interface(chip, chipnr); chip->select_chip(mtd, -1); if (ret) return ret; @@ -4037,7 +4041,7 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips, * For the other dies, nand_reset() will automatically switch to the * best mode for us. */ - ret = nand_setup_data_interface(chip); + ret = nand_setup_data_interface(chip, 0); if (ret) return ret; diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 90c6010..b1a6648 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -124,6 +124,8 @@ void nand_wait_ready(struct mtd_info *mtd); #define NAND_STATUS_READY 0x40 #define NAND_STATUS_WP 0x80 +#define NAND_DATA_IFACE_CHECK_ONLY -1 + /* * Constants for ECC_MODES */ @@ -807,7 +809,10 @@ nand_get_sdr_timings(const struct nand_data_interface *conf) * @read_retries: [INTERN] the number of read retry modes supported * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand - * @setup_data_interface: [OPTIONAL] setup the data interface and timing + * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If + * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this + * means the configuration should not be applied but + * only checked. * @bbt: [INTERN] bad block table pointer * @bbt_td: [REPLACEABLE] bad block table descriptor for flash * lookup. @@ -851,9 +856,8 @@ struct nand_chip { int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, int feature_addr, uint8_t *subfeature_para); int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode); - int (*setup_data_interface)(struct mtd_info *mtd, - const struct nand_data_interface *conf, - bool check_only); + int (*setup_data_interface)(struct mtd_info *mtd, int chipnr, + const struct nand_data_interface *conf); int chip_delay;