From patchwork Tue Nov 21 17:38:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 119376 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp5570454qgn; Tue, 21 Nov 2017 09:43:29 -0800 (PST) X-Google-Smtp-Source: AGs4zMZX0MHs+83gfXRrEd9ak1alQAJAheJXwCt5y9eYIATjGbCGC+31I42dPnRZjegCedBDNowy X-Received: by 10.80.182.138 with SMTP id d10mr25477506ede.131.1511286208640; Tue, 21 Nov 2017 09:43:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1511286208; cv=none; d=google.com; s=arc-20160816; b=m6cRK1FantPGh9aEA93DjQBLAehafPgSlVH1P7EQbzS8WfIJKaVqA9umjEoXbxfZt2 734UYtsn/fEVdv3JnJLeRoJ+R4jMDGyRK63s5k1fRK9AvcwGqSUxEnMbWFbK6JNAIhq/ 5PjVnM7sBIk71Exvc5GrAasFKZhJMa83K1vFN2yPRgpSWDgeo5HG78xG77CemNgFdaNZ 6XC6Yv6lNv48cQMKiPHZ+G/y0PDTJdH2O5W9Pp0ZxXzJtImaOXHvrz/SfPEuyZXb3WO/ GODEsp4hP7JC8gKoA/6qGA1w6/LfQH1lYJb/pirY5vK4uDMm9ldAcQVds+4IiKPL7pnO E/Eg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:dkim-filter:arc-authentication-results; bh=OvBmz2GmovKfNNyMv/ktD5rtDhfq7sX5RC8BwE+M3lc=; b=iB4jvqwohO7XwPU16RAA9cEstlwJIfWEiMNIF0ZSrzYUyxp7NjlsH1f92bEHNf82d/ be9lTHBXdmwsqGKdkI5qSE/9c8PMjnQYV4eZQmq0nvuLbgu18VsFt6hwW8NASNlN5f05 oEig0jhc7gtXtUEWWFnwE/ZOCHBcCr7oAjAqUVv2eX8mEF10+2ndTfzfCoGD1WwJ7IWM VLBLTlpqcMn4myROr6WtbUs21zb0WX+JlgNbFmNs3Xpqn3ZhqhRAVMM8AwHl6UA8KZj2 6ce2UtfWzOgi82N90BzRccvfTWhXGii5TS8usidPtKUUoEZd/U8XHKxjHAWlwnax50qN bJiw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=riwyoNjZ; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id b17si4348739edj.328.2017.11.21.09.43.28; Tue, 21 Nov 2017 09:43:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=riwyoNjZ; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 3283BC21EE6; Tue, 21 Nov 2017 17:42:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B611EC21FAC; Tue, 21 Nov 2017 17:39:29 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4CA47C21F88; Tue, 21 Nov 2017 17:39:08 +0000 (UTC) Received: from conuserg-07.nifty.com (conuserg-07.nifty.com [210.131.2.74]) by lists.denx.de (Postfix) with ESMTPS id 9C2E7C21F7C for ; Tue, 21 Nov 2017 17:39:06 +0000 (UTC) Received: from grover.sesame (FL1-125-199-20-195.osk.mesh.ad.jp [125.199.20.195]) (authenticated) by conuserg-07.nifty.com with ESMTP id vALHcbuB001225; Wed, 22 Nov 2017 02:38:46 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com vALHcbuB001225 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1511285926; bh=DpKGn6Wj5zs6PQKr8fg35WIIwCkjToj2FvuA864HU64=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=riwyoNjZ6FmErsx/VPVf7CuHnC+rWFJRiV5vRIXP4E40eSmk0GL3hHMt4/5ApdLug WYFJ03sddNXS3BfLaGlxqNhGHNSm5pgQUgFYA7SuonpULWA7qgPyujHPSOwp0YXN7x aw3kIXF933sqQ6vzoD4Mt52XiSsiWFRHBWw++KbGoSwzrpyWFdK3rroWOHvylw1+8H 5ZVvf9C612XC7bQLvGH4r3Z76DWryTIDA4DwHNQY9v+Myh0hItDO1lEizCmnHbX0PL 5OUlIx4Om3cCBBWo7Qw3qpDHtZML4QlRjd4gP5OuQ0hnZmHAp2aJbhk4Y+EA9Q3es4 MJthQC8y9Jm+g== X-Nifty-SrcIP: [125.199.20.195] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Wed, 22 Nov 2017 02:38:31 +0900 Message-Id: <1511285912-12452-22-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1511285912-12452-1-git-send-email-yamada.masahiro@socionext.com> References: <1511285912-12452-1-git-send-email-yamada.masahiro@socionext.com> Cc: Scott Wood Subject: [U-Boot] [PATCH 21/22] mtd: nand: introduce NAND_ROW_ADDR_3 flag X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Several drivers check ->chipsize to see if the third row address cycle is needed. Instead of embedding magic sizes such as 32MB, 128MB in drivers, introduce a new flag NAND_ROW_ADDR_3 for clean-up. Since nand_scan_ident() knows well about the device, it can handle this properly. The flag is set if the row address bit width is greater than 16. Delete comments such as "One more address cycle for ..." because intention is now clear enough from the code. Signed-off-by: Masahiro Yamada Acked-by: Wenyou Yang Signed-off-by: Boris Brezillon [Linux commit: 14157f861437ebe2d624b0a845b91bbdf8ca9a2d] --- drivers/mtd/nand/nand_base.c | 9 +++++---- include/linux/mtd/nand.h | 3 +++ 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 77a3f16..aca3231 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -634,8 +634,7 @@ static void nand_command(struct mtd_info *mtd, unsigned int command, chip->cmd_ctrl(mtd, page_addr, ctrl); ctrl &= ~NAND_CTRL_CHANGE; chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); - /* One more address cycle for devices > 32MiB */ - if (chip->chipsize > (32 << 20)) + if (chip->options & NAND_ROW_ADDR_3) chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); } chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); @@ -729,8 +728,7 @@ static void nand_command_lp(struct mtd_info *mtd, unsigned int command, chip->cmd_ctrl(mtd, page_addr, ctrl); chip->cmd_ctrl(mtd, page_addr >> 8, NAND_NCE | NAND_ALE); - /* One more address cycle for devices > 128MiB */ - if (chip->chipsize > (128 << 20)) + if (chip->options & NAND_ROW_ADDR_3) chip->cmd_ctrl(mtd, page_addr >> 16, NAND_NCE | NAND_ALE); } @@ -3889,6 +3887,9 @@ ident_done: chip->chip_shift += 32 - 1; } + if (chip->chip_shift - chip->page_shift > 16) + chip->options |= NAND_ROW_ADDR_3; + chip->badblockbits = 8; chip->erase = single_erase; diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 150e3b8..d1db34c 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -204,6 +204,9 @@ typedef enum { */ #define NAND_NEED_SCRAMBLING 0x00002000 +/* Device needs 3rd row address cycle */ +#define NAND_ROW_ADDR_3 0x00004000 + /* Options valid for Samsung large page devices */ #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG