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[81.169.180.215]) by mx.google.com with ESMTP id 44si5075939eds.62.2017.12.28.11.04.42; Thu, 28 Dec 2017 11:04:43 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=PiKtDPSQ; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id BE56EC21DBB; Thu, 28 Dec 2017 18:52:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id AE4CAC21E14; Thu, 28 Dec 2017 18:50:28 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B517EC21CB1; Thu, 28 Dec 2017 18:49:58 +0000 (UTC) Received: from mail-wm0-f65.google.com (mail-wm0-f65.google.com [74.125.82.65]) by lists.denx.de (Postfix) with ESMTPS id 55F68C21DDA for ; Thu, 28 Dec 2017 18:49:55 +0000 (UTC) Received: by mail-wm0-f65.google.com with SMTP id 64so44997077wme.3 for ; Thu, 28 Dec 2017 10:49:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=W3aaLbqI/MaiX5sYMhnL4aKeCAri3WIVr9Implx4W6o=; b=PiKtDPSQbvw5At3sI0wOZLHNt7/YUEVAGSMGskelgnLRI/wTkSqEHUhrb7UH98+qlz v0pQD9deoq685dkO8Vu7i3ve3Dv6DIAUC4Ru9lc1gExtW1Ac3TuV9PmP8GnmZnSUOKmW pgB5LImAsZD8TEcTh2GkK2242u2N+h3i5nz2g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=W3aaLbqI/MaiX5sYMhnL4aKeCAri3WIVr9Implx4W6o=; b=LQv3JraOaUDnkAFmEKNkFb98xAI1t49T0sMXgGuqLpRBStq57xoFADzF/oEv34Kmhx BFyi6nRSbnvhdT51xX2HTyREuxLl6gxmdwTb7M/xbeu6Lp6WkyLvhVI+SuuLvoWOf9L9 6LfA8aFIw/Kcv95/eN4oa2O88p8/7OoNGhgU+RMrAIoBbwgpuBkPTMsDAEvIsATBKcdy UtaCKNR67nBnOiOksRe9huZ5bJ4CXIGsT9OOOeTDc01Fw8jWhD7TGB2AObH+Q6Oexhbm gq/xdzm6FJGlTs92MbpGe1KMuozYKRKQ1q0VTqO0yhzHUE+qKn8PR0Oo6TTbl0B68+f/ 6Q3A== X-Gm-Message-State: AKGB3mIjDtJxDptsB19YoyLsFP66PU4LavyZh4VRqsRzFs7/k8q92PnX X/tgBxlTCtEb1lH8+YFtcVAgd2bfNKY= X-Received: by 10.80.243.136 with SMTP id g8mr41811736edm.42.1514486994731; Thu, 28 Dec 2017 10:49:54 -0800 (PST) Received: from localhost.localdomain ([109.255.42.2]) by smtp.gmail.com with ESMTPSA id x28sm35246579edd.0.2017.12.28.10.49.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 28 Dec 2017 10:49:54 -0800 (PST) From: Bryan O'Donoghue To: u-boot@lists.denx.de, brenomatheus@gmail.com Date: Thu, 28 Dec 2017 18:49:28 +0000 Message-Id: <1514486982-19059-10-git-send-email-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1514486982-19059-1-git-send-email-bryan.odonoghue@linaro.org> References: <1514486982-19059-1-git-send-email-bryan.odonoghue@linaro.org> Cc: Fabio Estevam Subject: [U-Boot] [PATCH v2 09/23] arm: imx: hab: Add IVT header definitions X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The various i.MX BootROMs containing the High Assurance Boot (HAB) block rely on a data structure called the Image Vector Table (IVT) to describe to the BootROM where to locate various data-structures used by HAB during authentication. This patch adds a definition of the IVT header for use in later patches, where we will break the current incorrect dependence on fixed offsets in favour of an IVT described parsing of incoming binaries. Signed-off-by: Bryan O'Donoghue Cc: Stefano Babic Cc: Fabio Estevam Cc: Peng Fan Cc: Albert Aribaud Cc: Sven Ebenfeld Cc: George McCollister Cc: Breno Matheus Lima --- arch/arm/include/asm/mach-imx/hab.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/include/asm/mach-imx/hab.h b/arch/arm/include/asm/mach-imx/hab.h index b2a8031..28cde38 100644 --- a/arch/arm/include/asm/mach-imx/hab.h +++ b/arch/arm/include/asm/mach-imx/hab.h @@ -10,6 +10,34 @@ #include +/* + * IVT header definitions + * Security Reference Manual for i.MX 7Dual and 7Solo Applications Processors, + * Rev. 0, 03/2017 + * Section : 6.7.1.1 + */ +#define IVT_HEADER_MAGIC 0xD1 +#define IVT_TOTAL_LENGTH 0x20 +#define IVT_HEADER_V1 0x40 +#define IVT_HEADER_V2 0x41 + +struct ivt_header { + uint8_t magic; + uint16_t length; + uint8_t version; +} __attribute__((packed)); + +struct ivt { + struct ivt_header hdr; /* IVT header above */ + uint32_t entry; /* Absolute address of first instruction */ + uint32_t reserved1; /* Reserved should be zero */ + uint32_t dcd; /* Absolute address of the image DCD */ + uint32_t boot; /* Absolute address of the boot data */ + uint32_t self; /* Absolute address of the IVT */ + uint32_t csf; /* Absolute address of the CSF */ + uint32_t reserved2; /* Reserved should be zero */ +}; + /* -------- start of HAB API updates ------------*/ /* The following are taken from HAB4 SIS */