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[81.169.180.215]) by mx.google.com with ESMTP id o91si1319744eda.349.2017.12.29.17.29.14; Fri, 29 Dec 2017 17:29:15 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=KECaG/jQ; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 9D809C21E08; Sat, 30 Dec 2017 01:14:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 35E38C21DA6; Sat, 30 Dec 2017 01:10:36 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 659F2C21E1E; Sat, 30 Dec 2017 01:09:18 +0000 (UTC) Received: from mail-wm0-f65.google.com (mail-wm0-f65.google.com [74.125.82.65]) by lists.denx.de (Postfix) with ESMTPS id BAC27C21DE8 for ; Sat, 30 Dec 2017 01:09:14 +0000 (UTC) Received: by mail-wm0-f65.google.com with SMTP id g75so50737664wme.0 for ; Fri, 29 Dec 2017 17:09:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=W3aaLbqI/MaiX5sYMhnL4aKeCAri3WIVr9Implx4W6o=; b=KECaG/jQUo4fTJQmrkscmCGVDh6bVWqkne9qE4NtFOpLoBAUy4FmVMU4RHze9KDlpR +QS/CfT3fGXa2081jaSw90d71Wy+kyWb55KVRTTTt8SIud63lozjo+BhAr7N7FHNL1NV o3bwaQbvCvc6mPb7Gxm4hoG0KQspHHIZkXc2E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=W3aaLbqI/MaiX5sYMhnL4aKeCAri3WIVr9Implx4W6o=; b=dxqtt9b17vF/M2KKwArWttU0ioMRnu9A3LmTM7PfU+Q56txROaV/4BF/F/yaS+P28r G/tbO4cPOvhvwBkmas5tLL+YsFyam3lG9KyMaHMvcyZCHpZAYoI0DAYX60CCt90LTg6k Y8vfOOmeo2FUwGn7XLg8+u7W/m4Zu/Tlf1J/Uel5YS8lyLNRzU0MehlD1HbVP8HH2wBx K8GdXG3eAzMcfnIbLnfbO+W6aObNmCtLUfP/xEA2cmuz083OvbJ7zXGwgU87WsCS/LVY wtztcdxhXFhznWd0Lop7jOzHwLQXD9fPXCvs9Ks6jriK7itKNk7yo1BwmwqwQiKqFkIb adbA== X-Gm-Message-State: AKGB3mKNr5/QJRHw2qgMkNHEH7zu5UQ9fDsln0N9HmCLhYp4H1rooOpM UKkq7oeJChpVtwLTyEoPeTST8IyMGYI= X-Received: by 10.80.150.70 with SMTP id y64mr46900199eda.223.1514596154184; Fri, 29 Dec 2017 17:09:14 -0800 (PST) Received: from localhost.localdomain ([109.255.42.2]) by smtp.gmail.com with ESMTPSA id f9sm26484148edm.83.2017.12.29.17.09.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 29 Dec 2017 17:09:13 -0800 (PST) From: Bryan O'Donoghue To: u-boot@lists.denx.de, brenomatheus@gmail.com Date: Sat, 30 Dec 2017 01:08:38 +0000 Message-Id: <1514596142-22050-10-git-send-email-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1514596142-22050-1-git-send-email-bryan.odonoghue@linaro.org> References: <1514596142-22050-1-git-send-email-bryan.odonoghue@linaro.org> Cc: Fabio Estevam Subject: [U-Boot] [PATCH v3 09/25] arm: imx: hab: Add IVT header definitions X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The various i.MX BootROMs containing the High Assurance Boot (HAB) block rely on a data structure called the Image Vector Table (IVT) to describe to the BootROM where to locate various data-structures used by HAB during authentication. This patch adds a definition of the IVT header for use in later patches, where we will break the current incorrect dependence on fixed offsets in favour of an IVT described parsing of incoming binaries. Signed-off-by: Bryan O'Donoghue Cc: Stefano Babic Cc: Fabio Estevam Cc: Peng Fan Cc: Albert Aribaud Cc: Sven Ebenfeld Cc: George McCollister Cc: Breno Matheus Lima --- arch/arm/include/asm/mach-imx/hab.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/include/asm/mach-imx/hab.h b/arch/arm/include/asm/mach-imx/hab.h index b2a8031..28cde38 100644 --- a/arch/arm/include/asm/mach-imx/hab.h +++ b/arch/arm/include/asm/mach-imx/hab.h @@ -10,6 +10,34 @@ #include +/* + * IVT header definitions + * Security Reference Manual for i.MX 7Dual and 7Solo Applications Processors, + * Rev. 0, 03/2017 + * Section : 6.7.1.1 + */ +#define IVT_HEADER_MAGIC 0xD1 +#define IVT_TOTAL_LENGTH 0x20 +#define IVT_HEADER_V1 0x40 +#define IVT_HEADER_V2 0x41 + +struct ivt_header { + uint8_t magic; + uint16_t length; + uint8_t version; +} __attribute__((packed)); + +struct ivt { + struct ivt_header hdr; /* IVT header above */ + uint32_t entry; /* Absolute address of first instruction */ + uint32_t reserved1; /* Reserved should be zero */ + uint32_t dcd; /* Absolute address of the image DCD */ + uint32_t boot; /* Absolute address of the boot data */ + uint32_t self; /* Absolute address of the IVT */ + uint32_t csf; /* Absolute address of the CSF */ + uint32_t reserved2; /* Reserved should be zero */ +}; + /* -------- start of HAB API updates ------------*/ /* The following are taken from HAB4 SIS */