From patchwork Thu Jan 25 10:51:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 125797 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp1032025ljf; Thu, 25 Jan 2018 03:03:10 -0800 (PST) X-Google-Smtp-Source: AH8x226xlnG9HGv99KMbj05aQdOS1u5C5cY91Zj/7Jk38V/7Us9lJ/rsNUlliB1EYJh/Ou7LTVKn X-Received: by 10.80.160.167 with SMTP id 36mr29249772edo.188.1516878190112; Thu, 25 Jan 2018 03:03:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516878190; cv=none; d=google.com; s=arc-20160816; b=KuoSL/SvsxDAfx3Xas2mjb1LOuHmGRxOQbf9WPDaQPCF2gBiX0OyIXGx37Ad+dF9Jw p6488WpN52+TLibKFxxeiFv18NKIXVCtinsjDz3bOmqOVr8AZOf8yx7N2mETJtvU59ne FLdzP36mZiqX+xIk90petyxXHYPpWtR96jtb3dXl2VXC78tEZ/ac3cwaZkcbdcJxkKYP 2v1HVqNTskOB6FvYlPtUvDnJU1A3R72y5ziwdptZ8fZLlCIrmohut0LiDoGm8Z8NnO9H 7j+4Ondqjo6FDDbmFcECNDrJdyM9tiUIcbTQkBifxyRkbOmealh/18edBE2VwIFW31uI jC7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=8Q91mM0QVuZCH8JhEjptnuLbtYxBpUnifhl6MlS4ht8=; b=LfagRLSXIhv0vGnhspnLX5VpKte4+ogEWZAw3wJYGfpZzEqvbnf88Qj6+MAMXRHQEj 6CIQLmQDpLatE3J+/3s7oZ6n2eXiO6SRkTlx5HBncJPtqTFx9LLfT+Eh1A1RA7Wp4aDy pjTFHwg5o5BrUWKaqYAjXq5GYn4Jv9zmXfm/kkGZnFyNl3/DTxFabVP2IAuVP3yWKPyI BEMs63B6+WaM0ojgsJ1jirIv5o5/4NbwnWdu5ebxz+UTvzLrpvu+DdHMbdJ8qv0t8jGf vHq/WGCZJvYFKLfkpeZaROjWoRcUGnWJNnX/TRU7lnwdpCyGKFByfVqiFDySZoXSjztA 20bw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=dtsvLKjW; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id l16si952986edd.55.2018.01.25.03.03.09; Thu, 25 Jan 2018 03:03:10 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=dtsvLKjW; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id A8A9DC223C3; Thu, 25 Jan 2018 10:56:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 525B2C223F6; Thu, 25 Jan 2018 10:53:10 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8A2C7C223B0; Thu, 25 Jan 2018 10:52:28 +0000 (UTC) Received: from lelnx194.ext.ti.com (lelnx194.ext.ti.com [198.47.27.80]) by lists.denx.de (Postfix) with ESMTPS id C8ED1C2237E for ; Thu, 25 Jan 2018 10:52:23 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id w0PAqKZv004248; Thu, 25 Jan 2018 04:52:20 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1516877540; bh=7MZV3qaF2ILhb+LR+Fk3sPBw0byly/j20nGAkxlNawI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=dtsvLKjWocunsbu33kAxWZYb5IaHrkpU+LvcKsbijLmFIluS1+njVVyAwj1AN5oVE bLe4Suff+TbXukO8dPr1/06W2SrlCQemI4gaZqk43d0GkxTjO013nyXHisuolTLscq gFLNXZvVwRVZEbymd8qp0sHKYXKHEQOxBQcvBQD8= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0PAqKui004935; Thu, 25 Jan 2018 04:52:20 -0600 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Thu, 25 Jan 2018 04:52:20 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Thu, 25 Jan 2018 04:52:20 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0PAqJ87000672; Thu, 25 Jan 2018 04:52:20 -0600 From: Jean-Jacques Hiblot To: , , , Date: Thu, 25 Jan 2018 11:51:44 +0100 Message-ID: <1516877510-14863-19-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1516877510-14863-1-git-send-email-jjhiblot@ti.com> References: <1516877510-14863-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Praneeth Bajjuri , u-boot@lists.denx.de, Vishal Mahaveer Subject: [U-Boot] [PATCH v2 18/24] ARM: OMAP5: set mmc clock frequency to 192MHz X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I Now that omap_hsmmc has support for hs200 mode, change the clock frequency to 192MHz. Also change the REFERENCE CLOCK frequency to 192MHz based on which the internal mmc clock divider is calculated. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- arch/arm/include/asm/arch-omap5/clock.h | 2 +- arch/arm/include/asm/omap_mmc.h | 4 ++++ arch/arm/mach-omap2/omap5/hw_data.c | 10 +++++----- 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index ee2e78b..3d718c0 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -135,7 +135,7 @@ /* CM_L3INIT_HSMMCn_CLKCTRL */ #define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) -#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25) +#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (3 << 25) /* CM_L3INIT_SATA_CLKCTRL */ #define SATA_CLKCTRL_OPTFCLKEN_MASK (1 << 8) diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index 6871f54..d604b79 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -199,7 +199,11 @@ struct omap_hsmmc_plat { #define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) /* Clock Configurations and Macros */ +#ifdef CONFIG_OMAP54XX +#define MMC_CLOCK_REFERENCE 192 /* MHz */ +#else #define MMC_CLOCK_REFERENCE 96 /* MHz */ +#endif /* DLL */ #define DLL_SWT (1 << 20) diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c index bb05e19..7fc3836 100644 --- a/arch/arm/mach-omap2/omap5/hw_data.c +++ b/arch/arm/mach-omap2/omap5/hw_data.c @@ -438,17 +438,17 @@ void enable_basic_clocks(void) setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, GPIO4_CLKCTRL_OPTFCLKEN_MASK); - /* Enable 96 MHz clock for MMC1 & MMC2 */ + /* Enable 192 MHz clock for MMC1 & MMC2 */ setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, HSMMC_CLKCTRL_CLKSEL_MASK); setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, HSMMC_CLKCTRL_CLKSEL_MASK); /* Set the correct clock dividers for mmc */ - setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, - HSMMC_CLKCTRL_CLKSEL_DIV_MASK); - setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, - HSMMC_CLKCTRL_CLKSEL_DIV_MASK); + clrbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, + HSMMC_CLKCTRL_CLKSEL_DIV_MASK); + clrbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, + HSMMC_CLKCTRL_CLKSEL_DIV_MASK); /* Select 32KHz clock as the source of GPTIMER1 */ setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,