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[81.169.180.215]) by mx.google.com with ESMTP id q15si1461485edd.343.2018.03.26.07.13.03; Mon, 26 Mar 2018 07:13:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=FDT4yCEp; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id D2D13C21F00; Mon, 26 Mar 2018 14:12:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A57C8C21F4A; Mon, 26 Mar 2018 14:12:06 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 844DCC21F52; Mon, 26 Mar 2018 14:11:53 +0000 (UTC) Received: from mail-wm0-f66.google.com (mail-wm0-f66.google.com [74.125.82.66]) by lists.denx.de (Postfix) with ESMTPS id 322CEC21EE7 for ; Mon, 26 Mar 2018 14:11:50 +0000 (UTC) Received: by mail-wm0-f66.google.com with SMTP id r82so15865156wme.0 for ; Mon, 26 Mar 2018 07:11:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FTY450W573+LAOAxsd6pMkGZOtoltz0Gr3RUeQrcG04=; b=FDT4yCEpXaFhwnG2Erj0hSBqGHlrCE2u86o6AWDnPpzC3Es597Ld/aC+Qw0vTa6VWu aJw3QAoAuWLFrtLYOvRJMsUfEIL/tL6fHL5Erx3WOzjtzZXp6/C96tc/IGyhRZaMl1qq C1CBZmHFMuO4wMKhq2EHpdWUeVL4EMhUzLADE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FTY450W573+LAOAxsd6pMkGZOtoltz0Gr3RUeQrcG04=; b=LPALAAzPEmf+58sWtV0XLFi8UjIoe42uYb7JXoo94cFauczgo1oBji+GykuxCkitxt mM7qrQ/G+fUR70mYBUqKErMJyz4DAeAHNTTdwlaTDml1zy1xBPcrFUMDzvVtkT2CDJz1 lDN8b7qciapWweQv5dXckXNCIWKOu+VvSi0ZZH2zDhELayAhL0S4uIRhAznkhus5ngjj wl6/haC8b6rzt4kXx3EKl1OH97lCV/L5cjq//AWXPRDK5RKITivTaqjz4FD4LelijRBl zJQZxGHWLLDtCPZXpHjMtHothOr2b1rfse74zzqo/l8cX/VgvRhCNaZk++/vf/4YAxzq dM6g== X-Gm-Message-State: AElRT7F1WwQAF27NlK6D4h1OOrjTl/H7a3AlEc6K7GDR1MI02Oc2CgEM bYNqBqoQiB9G5XHXZxLt+FPhWSUqtqk= X-Received: by 10.80.137.13 with SMTP id e13mr33029808ede.292.1522073509578; Mon, 26 Mar 2018 07:11:49 -0700 (PDT) Received: from localhost.localdomain ([109.255.42.2]) by smtp.gmail.com with ESMTPSA id a10sm10714045eda.71.2018.03.26.07.11.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 26 Mar 2018 07:11:48 -0700 (PDT) From: Bryan O'Donoghue To: U-Boot@lists.denx.de, sbabic@denx.de Date: Mon, 26 Mar 2018 15:11:44 +0100 Message-Id: <1522073505-13066-3-git-send-email-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1522073505-13066-1-git-send-email-bryan.odonoghue@linaro.org> References: <1522073505-13066-1-git-send-email-bryan.odonoghue@linaro.org> Cc: breno.lima@nxp.com, fabio.estevam@nxp.com, utkarsh.gupta@nxp.com Subject: [U-Boot] [PATCH v2 2/3] imximage: Specify default IVT offset in IMX image X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch adds BOOTROM_IVT_HDR_OFFSET at 0xC00. The BootROM expects to find the IVT header at a particular offset in an i.MX image. Defining the expected offset of the IVT header in the first-stage BootROM image format is of use of later stage authentication routines where those routines continue to follow the first-stage authentication layout. This patch defines the first stage offset with an upcoming set of BSP patches making use of that offset subsequently. Signed-off-by: Bryan O'Donoghue Cc: Utkarsh Gupta Cc: Breno Lima Cc: Fabio Estevam --- include/imximage.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/imximage.h b/include/imximage.h index 553b852..800fd63 100644 --- a/include/imximage.h +++ b/include/imximage.h @@ -14,6 +14,9 @@ #define APP_CODE_BARKER 0xB1 #define DCD_BARKER 0xB17219E9 +/* Specify the offset of the IVT in the IMX header as expected by BootROM */ +#define BOOTROM_IVT_HDR_OFFSET 0xC00 + /* * NOTE: This file must be kept in sync with arch/arm/include/asm/\ * mach-imx/imximage.cfg because tools/imximage.c can not