From patchwork Mon Mar 9 09:07:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ang, Chee Hong" X-Patchwork-Id: 243435 List-Id: U-Boot discussion From: chee.hong.ang at intel.com (chee.hong.ang at intel.com) Date: Mon, 9 Mar 2020 02:07:17 -0700 Subject: [PATCH v4 16/21] arm: socfpga: Add ATF support for Reset Manager driver In-Reply-To: <1583744842-24632-1-git-send-email-chee.hong.ang@intel.com> References: <1583744842-24632-1-git-send-email-chee.hong.ang@intel.com> Message-ID: <1583744842-24632-17-git-send-email-chee.hong.ang@intel.com> From: Chee Hong Ang In non-secure mode (EL2), Reset Manager driver calls the SMC/PSCI services provided by ATF to enable/disable the SOCFPGA bridges. Signed-off-by: Chee Hong Ang --- arch/arm/mach-socfpga/reset_manager_s10.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index c743077..c028e2d 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -5,10 +5,13 @@ */ #include +#include #include +#include #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -54,6 +57,12 @@ void socfpga_per_reset_all(void) void socfpga_bridges_reset(int enable) { +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) + u64 arg = enable; + + if (invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0)) + hang(); +#else if (enable) { /* clear idle request to all bridges */ setbits_le32(socfpga_get_sysmgr_addr() + @@ -94,6 +103,7 @@ void socfpga_bridges_reset(int enable) /* Disable NOC timeout */ writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT); } +#endif } /*