From patchwork Thu Apr 30 13:00:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Madalin Bucur \(OSS\)" X-Patchwork-Id: 238989 List-Id: U-Boot discussion From: madalin.bucur at oss.nxp.com (Madalin Bucur) Date: Thu, 30 Apr 2020 16:00:07 +0300 Subject: [PATCH 10/19] powerpc: dts: add QorIQ DPAA 1 FMan to P2041RDB In-Reply-To: <1588251616-14976-1-git-send-email-madalin.bucur@oss.nxp.com> References: <1588251616-14976-1-git-send-email-madalin.bucur@oss.nxp.com> Message-ID: <1588251616-14976-11-git-send-email-madalin.bucur@oss.nxp.com> Introduce the QorIQ DPAA 1 Frame Manager nodes in the P2041RDB device tree. The device tree fragments are copied over with little modification from the Linux kernel source code. Signed-off-by: Madalin Bucur --- arch/powerpc/dts/p2041rdb.dts | 98 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 97 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/dts/p2041rdb.dts b/arch/powerpc/dts/p2041rdb.dts index 6e9d9c0..9d59f9c 100644 --- a/arch/powerpc/dts/p2041rdb.dts +++ b/arch/powerpc/dts/p2041rdb.dts @@ -3,7 +3,7 @@ * P2041RDB Device Tree Source * * Copyright 2011 - 2015 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ /include/ "p2041.dtsi" @@ -15,4 +15,100 @@ #size-cells = <2>; interrupt-parent = <&mpic>; + aliases { + phy_rgmii_0 = &phy_rgmii_0; + phy_rgmii_1 = &phy_rgmii_1; + phy_sgmii_2 = &phy_sgmii_2; + phy_sgmii_3 = &phy_sgmii_3; + phy_sgmii_4 = &phy_sgmii_4; + phy_sgmii_1c = &phy_sgmii_1c; + phy_sgmii_1d = &phy_sgmii_1d; + phy_sgmii_1e = &phy_sgmii_1e; + phy_sgmii_1f = &phy_sgmii_1f; + phy_xgmii_2 = &phy_xgmii_2; + }; + + soc: soc at ffe000000 { + ranges = <0x00000000 0xf 0xfe000000 0x1000000>; + reg = <0xf 0xfe000000 0 0x00001000>; + + fman at 400000 { + ethernet at e0000 { + phy-handle = <&phy_sgmii_2>; + phy-connection-type = "sgmii"; + }; + + mdio at e1120 { + phy_rgmii_0: ethernet-phy at 0 { + reg = <0x0>; + }; + + phy_rgmii_1: ethernet-phy at 1 { + reg = <0x1>; + }; + + phy_sgmii_2: ethernet-phy at 2 { + reg = <0x2>; + }; + + phy_sgmii_3: ethernet-phy at 3 { + reg = <0x3>; + }; + + phy_sgmii_4: ethernet-phy at 4 { + reg = <0x4>; + }; + + phy_sgmii_1c: ethernet-phy at 1c { + reg = <0x1c>; + }; + + phy_sgmii_1d: ethernet-phy at 1d { + reg = <0x1d>; + }; + + phy_sgmii_1e: ethernet-phy at 1e { + reg = <0x1e>; + }; + + phy_sgmii_1f: ethernet-phy at 1f { + reg = <0x1f>; + }; + }; + + ethernet at e2000 { + phy-handle = <&phy_sgmii_3>; + phy-connection-type = "sgmii"; + }; + + ethernet at e4000 { + phy-handle = <&phy_sgmii_4>; + phy-connection-type = "sgmii"; + }; + + ethernet at e6000 { + phy-handle = <&phy_rgmii_1>; + phy-connection-type = "rgmii"; + }; + + ethernet at e8000 { + phy-handle = <&phy_rgmii_0>; + phy-connection-type = "rgmii"; + }; + + ethernet at f0000 { + phy-handle = <&phy_xgmii_2>; + phy-connection-type = "xgmii"; + }; + + mdio at f1000 { + phy_xgmii_2: ethernet-phy at 0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; + }; + }; + }; }; + +/include/ "p2041si-post.dtsi"