From patchwork Tue May 5 17:43:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Manoil X-Patchwork-Id: 245155 List-Id: U-Boot discussion From: claudiu.manoil at nxp.com (Claudiu Manoil) Date: Tue, 5 May 2020 20:43:07 +0300 Subject: [PATCH v4 5/6] arm: dts: ls1028a: adds Ethernet switch node and its dependencies In-Reply-To: <1588700588-8587-1-git-send-email-claudiu.manoil@nxp.com> References: <1588700588-8587-1-git-send-email-claudiu.manoil@nxp.com> Message-ID: <1588700588-8587-6-git-send-email-claudiu.manoil@nxp.com> From: Alex Marginean The definition follows the DSA binding in kernel and describes the switch, its ports and PHYs. ENETC PF6 is the 2nd Eth controller linked to the switch on LS1028A, it is not used in U-Boot and was disabled. Ethernet port aliases were also added to better manage the multitude of ports available now, and to enforce the order in which master and slave ports are probed. Signed-off-by: Alex Marginean Tested-by: Michael Walle Signed-off-by: Claudiu Manoil --- arch/arm/dts/fsl-ls1028a-rdb.dts | 36 +++++++++++++++++++++ arch/arm/dts/fsl-ls1028a.dtsi | 55 +++++++++++++++++++++++++++++++- 2 files changed, 90 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts index a8f40855b6..80c3907e94 100644 --- a/arch/arm/dts/fsl-ls1028a-rdb.dts +++ b/arch/arm/dts/fsl-ls1028a-rdb.dts @@ -129,9 +129,45 @@ phy-handle = <&rdb_phy0>; }; +ðsw_ports { + port at 0 { + status = "okay"; + phy-mode = "qsgmii"; + phy-handle = <&sw_phy0>; + }; + port at 1 { + status = "okay"; + phy-mode = "qsgmii"; + phy-handle = <&sw_phy1>; + }; + port at 2 { + status = "okay"; + phy-mode = "qsgmii"; + phy-handle = <&sw_phy2>; + }; + port at 3 { + status = "okay"; + phy-mode = "qsgmii"; + phy-handle = <&sw_phy3>; + }; +}; + &mdio0 { status = "okay"; rdb_phy0: phy at 2 { reg = <2>; }; + + sw_phy0: phy at 10 { + reg = <0x10>; + }; + sw_phy1: phy at 11 { + reg = <0x11>; + }; + sw_phy2: phy at 12 { + reg = <0x12>; + }; + sw_phy3: phy at 13 { + reg = <0x13>; + }; }; diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 5365bfb1a8..4de29149eb 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -14,6 +14,17 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + eth0 = &enetc0; + eth1 = &enetc1; + eth2 = &enetc2; + eth3 = &enetc6; + eth4 = &felix0; + eth5 = &felix1; + eth6 = &felix2; + eth7 = &felix3; + }; + sysclk: sysclk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -145,9 +156,51 @@ reg = <0x000300 0 0 0 0>; status = "disabled"; }; + ethsw: pci at 0,5 { + #address-cells=<0>; + #size-cells=<1>; + reg = <0x000500 0 0 0 0>; + + ethsw_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + felix0: port at 0 { + reg = <0>; + status = "disabled"; + label = "swp0"; + }; + felix1: port at 1 { + reg = <1>; + status = "disabled"; + label = "swp1"; + }; + felix2: port at 2 { + reg = <2>; + status = "disabled"; + label = "swp2"; + }; + felix3: port at 3 { + reg = <3>; + status = "disabled"; + label = "swp3"; + }; + port at 4 { + reg = <4>; + phy-mode = "internal"; + status = "okay"; + ethernet = <&enetc2>; + }; + port at 5 { + reg = <5>; + phy-mode = "internal"; + status = "disabled"; + }; + }; + }; enetc6: pci at 0,6 { reg = <0x000600 0 0 0 0>; - status = "okay"; + status = "disabled"; phy-mode = "internal"; }; };