From patchwork Sat May 9 14:25:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Tomer X-Patchwork-Id: 245342 List-Id: U-Boot discussion From: amittomer25 at gmail.com (Amit Singh Tomar) Date: Sat, 9 May 2020 19:55:09 +0530 Subject: [PATCH v1 1/7] clk: actions: Add Ethernet clocks In-Reply-To: <1589034315-19722-1-git-send-email-amittomer25@gmail.com> References: <1589034315-19722-1-git-send-email-amittomer25@gmail.com> Message-ID: <1589034315-19722-2-git-send-email-amittomer25@gmail.com> This commit adds clocks needed for ethernet operations for Actions OWL family of SoCs (S700 and S900). Signed-off-by: Amit Singh Tomar --- arch/arm/include/asm/arch-owl/regs_s700.h | 2 ++ arch/arm/include/asm/arch-owl/regs_s900.h | 4 ++++ drivers/clk/owl/clk_owl.c | 9 +++++++++ drivers/clk/owl/clk_owl.h | 2 -- 4 files changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-owl/regs_s700.h b/arch/arm/include/asm/arch-owl/regs_s700.h index 2f21c15cca8c..90459ae95eeb 100644 --- a/arch/arm/include/asm/arch-owl/regs_s700.h +++ b/arch/arm/include/asm/arch-owl/regs_s700.h @@ -53,4 +53,6 @@ #define CMU_CVBSPLL 0x00B8 #define CMU_SSTSCLK 0x00C0 +#define CMU_DEVCLKEN1_ETH BIT(23) + #endif diff --git a/arch/arm/include/asm/arch-owl/regs_s900.h b/arch/arm/include/asm/arch-owl/regs_s900.h index 9e9106ddaab9..084bc9b8c3fb 100644 --- a/arch/arm/include/asm/arch-owl/regs_s900.h +++ b/arch/arm/include/asm/arch-owl/regs_s900.h @@ -61,4 +61,8 @@ #define CMU_TVOUTPLLDEBUG0 (0x00EC) #define CMU_TVOUTPLLDEBUG1 (0x00FC) +#define CMU_DEVCLKEN1_ETH BIT(22) +#define CLK_ETHERNET CLK_ETH_MAC +#define CMU_ETHERNETPLL CMU_ASSISTPLL + #endif diff --git a/drivers/clk/owl/clk_owl.c b/drivers/clk/owl/clk_owl.c index 5607b2b7b516..b80862e17f51 100644 --- a/drivers/clk/owl/clk_owl.c +++ b/drivers/clk/owl/clk_owl.c @@ -85,6 +85,11 @@ int owl_clk_enable(struct clk *clk) /* Enable UART3 interface clock */ setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3); break; + case CLK_RMII_REF: + case CLK_ETHERNET: + setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_ETH); + setbits_le32(priv->base + CMU_ETHERNETPLL, 5); + break; default: return -EINVAL; } @@ -110,6 +115,10 @@ int owl_clk_disable(struct clk *clk) /* Disable UART3 interface clock */ clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3); break; + case CLK_RMII_REF: + case CLK_ETHERNET: + clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_ETH); + break; default: return -EINVAL; } diff --git a/drivers/clk/owl/clk_owl.h b/drivers/clk/owl/clk_owl.h index b8d33624c5f5..a2065a726d46 100644 --- a/drivers/clk/owl/clk_owl.h +++ b/drivers/clk/owl/clk_owl.h @@ -59,6 +59,4 @@ struct owl_clk_priv { #define CMU_DEVCLKEN1_UART5 BIT(21) #define CMU_DEVCLKEN1_UART3 BIT(11) -#define CMU_DEVCLKEN1_ETH_S700 BIT(23) - #endif