From patchwork Thu Jun 4 10:44:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sagar Shrikant Kadam X-Patchwork-Id: 241640 List-Id: U-Boot discussion From: sagar.kadam at sifive.com (Sagar Shrikant Kadam) Date: Thu, 4 Jun 2020 03:44:37 -0700 Subject: [PATCH v3 2/4] riscv: dts: hifive-unleashed-a00: add cpu aliases In-Reply-To: <1591267479-8900-1-git-send-email-sagar.kadam@sifive.com> References: <1591267479-8900-1-git-send-email-sagar.kadam@sifive.com> Message-ID: <1591267479-8900-3-git-send-email-sagar.kadam@sifive.com> Add cpu aliases to U-Boot specific dtsi for hifive-unleashed. Without aliases we see that the CPU device sequence numbers are set randomly and the cpu list/detail command will show it as follows: => cpu list 1: cpu at 0 rv64imac 0: cpu at 1 rv64imafdc 2: cpu at 2 rv64imafdc 3: cpu at 3 rv64imafdc 4: cpu at 4 rv64imafdc Seems like CPU probing with dm-model also relies on aliases as observed in case spi. The fu540-c000-u-boot.dtsi has cpu0/1/2/3/4 nodes and so adding corresponding aliases we can ensure that cpu devices are assigned proper sequence as follows: => cpu list 0: cpu at 0 rv64imac 1: cpu at 1 rv64imafdc 2: cpu at 2 rv64imafdc 3: cpu at 3 rv64imafdc 4: cpu at 4 rv64imafdc Signed-off-by: Sagar Shrikant Kadam Reviewed-by: Pragnesh Patel --- arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi index 9787332..9894260 100644 --- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi @@ -7,6 +7,11 @@ / { aliases { + cpu0 = &cpu0; + cpu1 = &cpu1; + cpu2 = &cpu2; + cpu3 = &cpu3; + cpu4 = &cpu4; spi0 = &qspi0; spi2 = &qspi2; };