From patchwork Tue Jun 9 10:51:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chaitanya Sakinam X-Patchwork-Id: 242000 List-Id: U-Boot discussion From: chaitanya.sakinam at nxp.com (Chaitanya Sakinam) Date: Tue, 9 Jun 2020 16:21:48 +0530 Subject: [PATCH] armv8: ls1012a: RGMII ports require internal delay Message-ID: <1591699908-21744-1-git-send-email-chaitanya.sakinam@nxp.com> The correct setting for the RGMII ports on LS1012ARDB is to enable delay on both Rx and Tx so the interface mode used should be PHY_INTERFACE_MODE_RGMII_ID Signed-off-by: Chaitanya Sakinam Signed-off-by: Anji J --- board/freescale/ls1012ardb/eth.c | 2 +- drivers/net/pfe_eth/pfe_eth.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c index 5edcfcf..ca15349 100644 --- a/board/freescale/ls1012ardb/eth.c +++ b/board/freescale/ls1012ardb/eth.c @@ -112,7 +112,7 @@ int pfe_eth_board_init(struct udevice *dev) /* MAC2 */ pfe_set_phy_address_mode(priv->gemac_port, CONFIG_PFE_EMAC2_PHY_ADDR, - PHY_INTERFACE_MODE_RGMII_TXID); + PHY_INTERFACE_MODE_RGMII_ID); } break; case 0x2208: diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c index 1b5d11e..6e22041 100644 --- a/drivers/net/pfe_eth/pfe_eth.c +++ b/drivers/net/pfe_eth/pfe_eth.c @@ -31,7 +31,7 @@ struct gemac_s gem_info[] = { /* phy iface */ .phy_address = CONFIG_PFE_EMAC2_PHY_ADDR, - .phy_mode = PHY_INTERFACE_MODE_RGMII_TXID, + .phy_mode = PHY_INTERFACE_MODE_RGMII_ID, }, };