From patchwork Mon Jun 22 12:27:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sagar Shrikant Kadam X-Patchwork-Id: 242743 List-Id: U-Boot discussion From: sagar.kadam at sifive.com (Sagar Shrikant Kadam) Date: Mon, 22 Jun 2020 05:27:52 -0700 Subject: [PATCH 1/5] dt-bindings: prci: add indexes for reset signals available in prci In-Reply-To: <1592828876-7724-1-git-send-email-sagar.kadam@sifive.com> References: <1592828876-7724-1-git-send-email-sagar.kadam@sifive.com> Message-ID: <1592828876-7724-2-git-send-email-sagar.kadam@sifive.com> Add bit indexes for reset signals within the PRCI module on FU540-C000 SoC. The DDR and ethernet sub-system's have reset signals indicated by these reset indexes. Signed-off-by: Sagar Shrikant Kadam Reviewed-by: Pragnesh Patel Reviewed-by: Bin Meng --- include/dt-bindings/clock/sifive-fu540-prci.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt-bindings/clock/sifive-fu540-prci.h index 6a0b70a..1c03b09 100644 --- a/include/dt-bindings/clock/sifive-fu540-prci.h +++ b/include/dt-bindings/clock/sifive-fu540-prci.h @@ -15,4 +15,12 @@ #define PRCI_CLK_GEMGXLPLL 2 #define PRCI_CLK_TLCLK 3 +/* Reset bit indexes to be used by driver */ +#define PRCI_RST_DDR_CTRL_N 0 +#define PRCI_RST_DDR_AXI_N 1 +#define PRCI_RST_DDR_AHB_N 2 +#define PRCI_RST_DDR_PHY_N 3 +/* bit 4 is reserved bit */ +#define PRCI_RST_RSVD_N 4 +#define PRCI_RST_GEMGXL_N 5 #endif