From patchwork Tue Jun 23 05:29:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 242783 List-Id: U-Boot discussion From: bmeng.cn at gmail.com (Bin Meng) Date: Mon, 22 Jun 2020 22:29:44 -0700 Subject: [PATCH 3/5] riscv: Do not build reset.c if SYSRESET is on In-Reply-To: <1592890186-18082-1-git-send-email-bmeng.cn@gmail.com> References: <1592890186-18082-1-git-send-email-bmeng.cn@gmail.com> Message-ID: <1592890186-18082-3-git-send-email-bmeng.cn@gmail.com> From: Bin Meng SYSRESET uclass driver already provides all the reset APIs, hence exclude our own ad-hoc reset.c implementation. Signed-off-by: Bin Meng Reviewed-by: Sagar Kadam Reviewed-by: Pragnesh Patel --- arch/riscv/lib/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index b5e9324..6c503ff 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -20,7 +20,9 @@ obj-$(CONFIG_SBI) += sbi.o obj-$(CONFIG_SBI_IPI) += sbi_ipi.o endif obj-y += interrupts.o +ifeq ($(CONFIG_$(SPL_)SYSRESET),) obj-y += reset.o +endif obj-y += setjmp.o obj-$(CONFIG_$(SPL_)SMP) += smp.o obj-$(CONFIG_SPL_BUILD) += spl.o