From patchwork Mon Jul 13 16:59:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wasim Khan X-Patchwork-Id: 241426 List-Id: U-Boot discussion From: wasim.khan at nxp.com (Wasim Khan) Date: Mon, 13 Jul 2020 22:29:09 +0530 Subject: [PATCH 06/12] arm: dts: ls1088a: add label to pcie nodes in dts In-Reply-To: <1594659555-12669-1-git-send-email-wasim.khan@nxp.com> References: <1594659555-12669-1-git-send-email-wasim.khan@nxp.com> Message-ID: <1594659555-12669-7-git-send-email-wasim.khan@nxp.com> add label to pcie nodes in dts Signed-off-by: Wasim Khan --- arch/arm/dts/fsl-ls1088a.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index bf303c6..8de7998 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -2,7 +2,7 @@ /* * NXP ls1088a SOC common device tree source * - * Copyright 2017 NXP + * Copyright 2017, 2020 NXP */ / { @@ -129,7 +129,7 @@ dr_mode = "host"; }; - pcie at 3400000 { + pcie1: pcie at 3400000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ 0x00 0x03480000 0x0 0x80000 /* lut registers */ @@ -145,7 +145,7 @@ 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie at 3500000 { + pcie2: pcie at 3500000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */ 0x00 0x03580000 0x0 0x80000 /* lut registers */ @@ -161,7 +161,7 @@ 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie at 3600000 { + pcie3: pcie at 3600000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */ 0x00 0x03680000 0x0 0x80000 /* lut registers */