From patchwork Fri Sep 14 08:06:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AKASHI Takahiro X-Patchwork-Id: 146682 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp407209ljw; Fri, 14 Sep 2018 01:06:51 -0700 (PDT) X-Google-Smtp-Source: ANB0VdaITJ9g1rC7Gn/19Dlb5e+k5Pg1FtnogNO61eG/Hql7dllAJQpGR+n16aQEiJh9vC/KvPi7 X-Received: by 2002:a50:a844:: with SMTP id j62-v6mr18745485edc.210.1536912411760; Fri, 14 Sep 2018 01:06:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1536912411; cv=none; d=google.com; s=arc-20160816; b=Ek4qTsddtq7VLs2J45mjucMI4asq3VRE0Cw5EItdNJnwnUOxNH9+mlSoIR1Z/fqZFq BUSJpScBRKYwtYJf2RdLrr88JvKe0u9hXUSGARSW9W1xLAtw3ARQUpwKmDuKLtQk3Sp4 RKuRuW+6lbB+EUaAtLX0WGB+vfV/MePhCaeXWFx/fZmt0qMfvmPKDspP4kfqncipXIkb 6XV8R6APxE7sp4rqTw+f5aJYZuvIlCPM4OWQ7FR9vMycutWYhVtDlrkxtFYLr4NEoTfe WEOGFnUWkvBlTGGtzrEHC1+tYfywu3wTU5Ql6lzpW92zVYjqxtwpusjyZCRBMyoGhxOZ O47w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature; bh=cAJq+1rVjrz+JgtINjM54IPbbQindv1RLlred58EXaA=; b=RAeV/1q1lmqM6BD6pFo1mNqTVg9EJi06NJdUDsb/rUT4Cl+Sftcyit+8uOvPRt0gM/ QcEfqHsI9m1LO75l/aSEN4bn3ebknyplBfKQPiFUsuDsH5DXlApnZSRz+pd+bAHAwNje pjzZ0jVNikfikISDm5oJ0EZwL2cXHHjiqvofSiXCPLCqrcZCB9v8SCl9ifDUqLy7o5Vi jIXOi7wWLGaJ17+mo693F10D4V6phcUuNt77YenlbH9ZlGjFJS77aEMIXY/ULqM8yzH3 /zEYt9+3xLH+lRn/1onBeJ6JmcR6GB0zbUt7HHx//pY8hR80tbl8V2ucEfuNXxwSwBJr qxzA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=MrJi+jkx; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id l60-v6si3597327ede.26.2018.09.14.01.06.51; Fri, 14 Sep 2018 01:06:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=MrJi+jkx; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 061E9C2200E; Fri, 14 Sep 2018 08:06:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 21A2CC2200C; Fri, 14 Sep 2018 08:06:37 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id ACC2AC22048; Fri, 14 Sep 2018 08:06:30 +0000 (UTC) Received: from mail-pl1-f195.google.com (mail-pl1-f195.google.com [209.85.214.195]) by lists.denx.de (Postfix) with ESMTPS id E9707C2200C for ; Fri, 14 Sep 2018 08:06:26 +0000 (UTC) Received: by mail-pl1-f195.google.com with SMTP id g2-v6so3847926plo.2 for ; Fri, 14 Sep 2018 01:06:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=m7vfyg3dwrnXJo15knoCvf4c4DmD2lqaScI6rcYTrhc=; b=MrJi+jkxi1Hf4yxUbvnDj6XoLNvR1EhdIq1HQikiNpTmPEugD+CATL+JBHgVf8XS6N mQ54Y6WRt1A/lwcfNTCPTAJ1Hib0MHnbxObxRfk0renyC4R+XVnE30IRhtxxFeNgC3pt lT5ves7ArBaZgGfnHmqEdbm6vlKNyLOYl4YqY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=m7vfyg3dwrnXJo15knoCvf4c4DmD2lqaScI6rcYTrhc=; b=oAw35Ma3qVeovjQmsB7lEOrTfPall9dRQAFw/VmEO0li89C/MQ0mkY0M2GKXPIJgEb RmzJl9z/9m2pM/ti859xCJbttath9YACNMEgaCe3aK+OOyHy2tDkaSDC+XouuTmCO9we kXr84pX51JWr2jnYfBgk1Qua3+hpPG5yWgmy8NepIbNCWFT2EplVyg8CL1j7PLR0nmCq 3Ac+frDoqrSqj983xzgCnuCty7JTh+gmMntJqN38QGuWvhsAjb8Nwo10cHmyDDpglUcv lkaU22bph8BqQ6Lbrmg7Xe0LGqg80t24F8f5y3+okTD7YayKNm2QnPJWvSiDoKQnpwu6 P7vw== X-Gm-Message-State: APzg51CcnDImQqZxnNL6qV/FKBvt//mKu/Z9kayafmFIQw7NeMmbPWpb 4nMk9UNR/Tn+QaLi47/wlrjbBQ== X-Received: by 2002:a17:902:8c82:: with SMTP id t2-v6mr11028604plo.241.1536912385548; Fri, 14 Sep 2018 01:06:25 -0700 (PDT) Received: from linaro.org ([121.95.100.191]) by smtp.googlemail.com with ESMTPSA id o20-v6sm17376504pfj.35.2018.09.14.01.06.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Sep 2018 01:06:25 -0700 (PDT) From: "Akashi, Takahiro" To: trini@konsulko.com, sjg@chromium.org, tuomas.tynkkynen@iki.fi Date: Fri, 14 Sep 2018 17:06:53 +0900 Message-Id: <20180914080654.29035-2-takahiro.akashi@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180914080654.29035-1-takahiro.akashi@linaro.org> References: <20180914080654.29035-1-takahiro.akashi@linaro.org> Cc: xypron.glpk@gmx.de, agraf@suse.de, u-boot@lists.denx.de Subject: [U-Boot] [PATCH v4 1/2] rtc: pl031: convert the driver to driver model X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: AKASHI Takahiro With this patch, PL031 driver is converted to driver-model-compliant driver. In addition, CONFIG_SYS_RTC_PL031_BASE is no longer valid. Signed-off-by: AKASHI Takahiro --- drivers/rtc/pl031.c | 126 ++++++++++++++++++++++------------- include/configs/qemu-arm.h | 3 - scripts/config_whitelist.txt | 1 - 3 files changed, 80 insertions(+), 50 deletions(-) diff --git a/drivers/rtc/pl031.c b/drivers/rtc/pl031.c index 8955805e3bc1..8bf04f26a375 100644 --- a/drivers/rtc/pl031.c +++ b/drivers/rtc/pl031.c @@ -8,13 +8,11 @@ #include #include +#include +#include #include - -#if defined(CONFIG_CMD_DATE) - -#ifndef CONFIG_SYS_RTC_PL031_BASE -#error CONFIG_SYS_RTC_PL031_BASE is not defined! -#endif +#include +#include /* * Register definitions @@ -30,78 +28,114 @@ #define RTC_CR_START (1 << 0) -#define RTC_WRITE_REG(addr, val) \ - (*(volatile unsigned int *)(CONFIG_SYS_RTC_PL031_BASE + (addr)) = (val)) -#define RTC_READ_REG(addr) \ - (*(volatile unsigned int *)(CONFIG_SYS_RTC_PL031_BASE + (addr))) +struct pl031_platdata { + phys_addr_t base; +}; -static int pl031_initted = 0; +static inline u32 pl031_read_reg(struct udevice *dev, int reg) +{ + struct pl031_platdata *pdata = dev_get_platdata(dev); -/* Enable RTC Start in Control register*/ -void rtc_init(void) + return readl(pdata->base + reg); +} + +static inline u32 pl031_write_reg(struct udevice *dev, int reg, u32 value) { - RTC_WRITE_REG(RTC_CR, RTC_CR_START); + struct pl031_platdata *pdata = dev_get_platdata(dev); - pl031_initted = 1; + return writel(value, pdata->base + reg); } /* - * Reset the RTC. We set the date back to 1970-01-01. + * Probe RTC device + */ +static int pl031_probe(struct udevice *dev) +{ + /* Enable RTC Start in Control register*/ + pl031_write_reg(dev, RTC_CR, RTC_CR_START); + + return 0; +} + +/* + * Get the current time from the RTC */ -void rtc_reset(void) +static int pl031_get(struct udevice *dev, struct rtc_time *tm) { - RTC_WRITE_REG(RTC_LR, 0x00); - if(!pl031_initted) - rtc_init(); + unsigned long tim; + + if (!tm) + return -EINVAL; + + tim = pl031_read_reg(dev, RTC_DR); + + rtc_to_tm(tim, tm); + + debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, + tm->tm_hour, tm->tm_min, tm->tm_sec); + + return 0; } /* * Set the RTC -*/ -int rtc_set(struct rtc_time *tmp) + */ +static int pl031_set(struct udevice *dev, const struct rtc_time *tm) { unsigned long tim; - if(!pl031_initted) - rtc_init(); + if (!tm) + return -EINVAL; - if (tmp == NULL) { - puts("Error setting the date/time\n"); - return -1; - } + debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, + tm->tm_hour, tm->tm_min, tm->tm_sec); /* Calculate number of seconds this incoming time represents */ - tim = rtc_mktime(tmp); + tim = rtc_mktime(tm); - RTC_WRITE_REG(RTC_LR, tim); + pl031_write_reg(dev, RTC_LR, tim); - return -1; + return 0; } /* - * Get the current time from the RTC + * Reset the RTC. We set the date back to 1970-01-01. */ -int rtc_get(struct rtc_time *tmp) +static int pl031_reset(struct udevice *dev) { - ulong tim; + pl031_write_reg(dev, RTC_LR, 0); - if(!pl031_initted) - rtc_init(); + return 0; +} - if (tmp == NULL) { - puts("Error getting the date/time\n"); - return -1; - } +static const struct rtc_ops pl031_ops = { + .get = pl031_get, + .set = pl031_set, + .reset = pl031_reset, +}; - tim = RTC_READ_REG(RTC_DR); +static const struct udevice_id pl031_ids[] = { + { .compatible = "arm,pl031" }, + { } +}; - rtc_to_tm(tim, tmp); +static int pl031_ofdata_to_platdata(struct udevice *dev) +{ + struct pl031_platdata *pdata = dev_get_platdata(dev); - debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + pdata->base = dev_read_addr(dev); return 0; } -#endif +U_BOOT_DRIVER(rtc_pl031) = { + .name = "rtc-pl031", + .id = UCLASS_RTC, + .of_match = pl031_ids, + .probe = pl031_probe, + .ofdata_to_platdata = pl031_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct pl031_platdata), + .ops = &pl031_ops, +}; diff --git a/include/configs/qemu-arm.h b/include/configs/qemu-arm.h index 913ff4f2636f..ba106247dc6f 100644 --- a/include/configs/qemu-arm.h +++ b/include/configs/qemu-arm.h @@ -23,9 +23,6 @@ /* For block devices, QEMU emulates an ICH9 AHCI controller over PCI */ #define CONFIG_SYS_SCSI_MAX_SCSI_ID 6 -/* QEMU emulates the ARM AMBA PL031 RTC */ -#define CONFIG_SYS_RTC_PL031_BASE 0x09010000 - /* Environment options */ #define CONFIG_ENV_SIZE SZ_64K diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index fc37099cbe0e..6168684daabf 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -4070,7 +4070,6 @@ CONFIG_SYS_RSTC_RMR_VAL CONFIG_SYS_RTC_BUS_NUM CONFIG_SYS_RTC_CNT CONFIG_SYS_RTC_OSCILLATOR -CONFIG_SYS_RTC_PL031_BASE CONFIG_SYS_RTC_REG_BASE_ADDR CONFIG_SYS_RTC_SETUP CONFIG_SYS_RV3029_TCR