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[81.169.180.215]) by mx.google.com with ESMTP id f19-v6si3298098edd.409.2018.11.13.04.19.20; Tue, 13 Nov 2018 04:19:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=O57vSiu4; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 1D621C224DE; Tue, 13 Nov 2018 12:17:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 72A8EC224F6; Tue, 13 Nov 2018 12:15:33 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B78C6C21EC8; Tue, 13 Nov 2018 08:52:03 +0000 (UTC) Received: from mail-wm1-f68.google.com (mail-wm1-f68.google.com [209.85.128.68]) by lists.denx.de (Postfix) with ESMTPS id 61894C21EC8 for ; Tue, 13 Nov 2018 08:52:03 +0000 (UTC) Received: by mail-wm1-f68.google.com with SMTP id f2-v6so10543466wme.3 for ; Tue, 13 Nov 2018 00:52:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/CmlmCmViZQAz4cyHIO2o3IkVmiv6Tq2TnwqaDNM8mQ=; b=O57vSiu4LATMutYg1Mw3flF97GjJAPx91AnVjQFrEezdAF4RTDLDPv1hhP4qcEvvqs pMQP1Z2pPRYAd1nACbhAKGqRzUKyx1tHiyzG+meCssh3fSYe0qJorWXYUPLPmFA+zqh6 2ISwswNUwoNpD7XyO7x9DMBy8mx8OoWRb98Ro= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/CmlmCmViZQAz4cyHIO2o3IkVmiv6Tq2TnwqaDNM8mQ=; b=Ox06p1hwBRgma2vV8yUf+wN6QXv6+AG9bgNn0v6OZejKBj8LaZPbpR0EtElDvBoYB9 neSl3sMODKVht+qX7XYy/zGBZU2j/KHcKFxdbfcrs/s5uJUP2H+rd5iS6tDvYu0XKeF4 Eyx61ZFAm9skHI4futQxw0Fcj9xVRiCuHnjjDvOMl/gTEkuYVvX4X/Cv9dZcJBM30ek5 667b7Dt4Y4km0+HiusaEITA0v3CnngcBjGEVMbZq0s8nmHmlOgSfc4dUm8nqj/NWesRh gI2+KpR2MAfu1f2lvve5eATf2PreATL++lT/G3NHFWLlxK8v8Mo5ImZHWm1D7PCnb6HD qDmA== X-Gm-Message-State: AGRZ1gKlVg8hGp7sChbGEIka/m1XDIT8RG5poqX7U0sZQRdN8YxRRFzj fPxhVx6P4teWUki8118oMHjCyQ== X-Received: by 2002:a1c:9a0d:: with SMTP id c13-v6mr2302660wme.65.1542099123032; Tue, 13 Nov 2018 00:52:03 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:1047:8145:8cab:bca7:b2f2:d2bb]) by smtp.gmail.com with ESMTPSA id d18-v6sm4235544wre.25.2018.11.13.00.52.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 13 Nov 2018 00:52:02 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: patrick.delaunay@st.com, albert.u.boot@aribaud.net, sjg@chromium.org, christophe.kerello@st.com, patrice.chotard@st.com Date: Tue, 13 Nov 2018 09:51:49 +0100 Message-Id: <20181113085151.32368-3-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20181113085151.32368-1-benjamin.gaignard@st.com> References: <20181113085151.32368-1-benjamin.gaignard@st.com> X-Mailman-Approved-At: Tue, 13 Nov 2018 12:15:27 +0000 Cc: uboot-stm32@st-md-mailman.stormreply.com, u-boot@lists.denx.de Subject: [U-Boot] [PATCH 2/4] clk: stm32: add hardware spinlock clock X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Benjamin Gaignard Add hardware spinlock in the list of the clocks. Signed-off-by: Benjamin Gaignard --- drivers/clk/clk_stm32mp1.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 6a8c7b754f..b7c5d34fe0 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -104,6 +104,7 @@ #define RCC_MP_APB2ENSETR 0XA08 #define RCC_MP_APB3ENSETR 0xA10 #define RCC_MP_AHB2ENSETR 0xA18 +#define RCC_MP_AHB3ENSETR 0xA20 #define RCC_MP_AHB4ENSETR 0xA28 /* used for most of SELR register */ @@ -534,6 +535,8 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),