From patchwork Mon Jan 6 14:13:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 239164 List-Id: U-Boot discussion From: marex at denx.de (Marek Vasut) Date: Mon, 6 Jan 2020 15:13:46 +0100 Subject: [PATCH V3 3/3] watchdog: designware: Optionally fetch clock and reset from DT In-Reply-To: <20200106141346.47008-1-marex@denx.de> References: <20200106141346.47008-1-marex@denx.de> Message-ID: <20200106141346.47008-3-marex@denx.de> Add optional support for fetching watchdog clock rate from DT and ungating reset via reset framework. This is optional as not all platforms using DW WDT support the clock and reset frameworks yet. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dalon Westergreen Cc: Dinh Nguyen Cc: Jagan Teki Cc: Ley Foon Tan Cc: Philipp Tomisch Cc: Simon Goldschmidt Cc: Tien Fong Chee Reviewed-by: Jagan Teki Tested-by: Jagan Teki # roc-rk3399-pc --- V2: - New patch V3: - Add reset handling --- drivers/watchdog/designware_wdt.c | 40 +++++++++++++++++++++++++------ 1 file changed, 33 insertions(+), 7 deletions(-) diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c index a7b735979a..1024a04596 100644 --- a/drivers/watchdog/designware_wdt.c +++ b/drivers/watchdog/designware_wdt.c @@ -3,8 +3,10 @@ * Copyright (C) 2013 Altera Corporation */ +#include #include #include +#include #include #include #include @@ -15,11 +17,11 @@ #define DW_WDT_CR_EN_OFFSET 0x00 #define DW_WDT_CR_RMOD_OFFSET 0x01 -#define DW_WDT_CR_RMOD_VAL 0x00 #define DW_WDT_CRR_RESTART_VAL 0x76 struct designware_wdt_priv { void __iomem *base; + unsigned int clk_khz; }; /* @@ -42,9 +44,7 @@ static int designware_wdt_settimeout(void __iomem *base, unsigned int clk_khz, static void designware_wdt_enable(void __iomem *base) { - writel((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) | - BIT(DW_WDT_CR_EN_OFFSET), - base + DW_WDT_CR); + writel(BIT(DW_WDT_CR_EN_OFFSET), base + DW_WDT_CR); } static unsigned int designware_wdt_is_enabled(void __iomem *base) @@ -93,8 +93,7 @@ static int designware_wdt_stop(struct udevice *dev) struct designware_wdt_priv *priv = dev_get_priv(dev); designware_wdt_reset(dev); - writel(DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET, - priv->base + DW_WDT_CR); + writel(0, priv->base + DW_WDT_CR); return 0; } @@ -106,7 +105,7 @@ static int designware_wdt_start(struct udevice *dev, u64 timeout, ulong flags) designware_wdt_stop(dev); /* set timer in miliseconds */ - designware_wdt_settimeout(priv->base, CONFIG_DW_WDT_CLOCK_KHZ, timeout); + designware_wdt_settimeout(priv->base, priv->clk_khz, timeout); designware_wdt_enable(priv->base); @@ -117,11 +116,38 @@ static int designware_wdt_start(struct udevice *dev, u64 timeout, ulong flags) static int designware_wdt_probe(struct udevice *dev) { struct designware_wdt_priv *priv = dev_get_priv(dev); + __maybe_unused int ret; priv->base = dev_remap_addr(dev); if (!priv->base) return -EINVAL; +#if CONFIG_IS_ENABLED(CLK) + struct clk clk; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return ret; + + priv->clk_khz = clk_get_rate(&clk); + if (!priv->clk_khz) + return -EINVAL; +#else + priv->clk_khz = CONFIG_DW_WDT_CLOCK_KHZ; +#endif + +#if CONFIG_IS_ENABLED(DM_RESET) + struct reset_ctl_bulk resets; + + ret = reset_get_bulk(dev, &resets); + if (ret) + return ret; + + ret = reset_deassert_bulk(&resets); + if (ret) + return ret; +#endif + /* reset to disable the watchdog */ return designware_wdt_stop(dev); }