From patchwork Thu Jan 9 10:07:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 239302 List-Id: U-Boot discussion From: marex at denx.de (Marek Vasut) Date: Thu, 9 Jan 2020 11:07:53 +0100 Subject: [PATCH 2/3] mtd: rawnand: denali: Allow operation without clock driver In-Reply-To: <20200109100754.1007705-1-marex@denx.de> References: <20200109100754.1007705-1-marex@denx.de> Message-ID: <20200109100754.1007705-2-marex@denx.de> The SoCFPGA Gen5 does not have a clock driver yet, let the NAND driver work without a clock driver by falling back to the default frequencies. Signed-off-by: Marek Vasut Cc: Masahiro Yamada --- drivers/mtd/nand/raw/denali_dt.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c index 0ce81324b9..2c9e249ab6 100644 --- a/drivers/mtd/nand/raw/denali_dt.c +++ b/drivers/mtd/nand/raw/denali_dt.c @@ -62,7 +62,6 @@ static int denali_dt_probe(struct udevice *dev) { struct denali_nand_info *denali = dev_get_priv(dev); const struct denali_dt_data *data; - struct clk clk, clk_x, clk_ecc; struct resource res; int ret; @@ -87,11 +86,14 @@ static int denali_dt_probe(struct udevice *dev) denali->host = devm_ioremap(dev, res.start, resource_size(&res)); +#if CONFIG_IS_ENABLED(CLK) + struct clk clk, clk_x, clk_ecc; + ret = clk_get_by_name(dev, "nand", &clk); if (ret) ret = clk_get_by_index(dev, 0, &clk); if (ret) - return ret; + clk.dev = NULL; ret = clk_get_by_name(dev, "nand_x", &clk_x); if (ret) @@ -117,10 +119,12 @@ static int denali_dt_probe(struct udevice *dev) return ret; } - if (clk_x.dev) { + if (clk.dev && clk_x.dev) { denali->clk_rate = clk_get_rate(&clk); denali->clk_x_rate = clk_get_rate(&clk_x); - } else { + } else +#endif + { /* * Hardcode the clock rates for the backward compatibility. * This works for both SOCFPGA and UniPhier.