[v4,17/17] riscv: Add Sipeed Maix support

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 659d98e33d..709a44759c 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -20,6 +20,9 @@  config TARGET_QEMU_VIRT
 config TARGET_SIFIVE_FU540
 	bool "Support SiFive FU540 Board"
 
+config TARGET_SIPEED_MAIX
+	bool "Support Sipeed Maix Board"
+
 endchoice
 
 config SYS_ICACHE_OFF
@@ -53,6 +56,7 @@  source "board/AndesTech/ax25-ae350/Kconfig"
 source "board/emulation/qemu-riscv/Kconfig"
 source "board/microchip/mpfs_icicle/Kconfig"
 source "board/sifive/fu540/Kconfig"
+source "board/sipeed/maix/Kconfig"
 
 # platform-specific options below
 source "arch/riscv/cpu/ax25/Kconfig"
diff --git a/board/sipeed/maix/Kconfig b/board/sipeed/maix/Kconfig
new file mode 100644
index 0000000000..580c7f06ba
--- /dev/null
+++ b/board/sipeed/maix/Kconfig
@@ -0,0 +1,56 @@ 
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2019-20 Sean Anderson <seanga2 at gmail.com>
+
+if TARGET_SIPEED_MAIX
+
+config SYS_BOARD
+	default "maix"
+
+config SYS_VENDOR
+	default "sipeed"
+
+config SYS_CPU
+	default "generic"
+
+config SYS_CONFIG_NAME
+	default "sipeed-maix"
+
+config SYS_TEXT_BASE
+	default 0x80000000
+
+config DEFAULT_DEVICE_TREE
+	default "k210-maix-bit"
+
+config NR_CPUS
+	default 2
+
+config NR_DRAM_BANKS
+	default 3
+
+config SF_DEFAULT_BUS
+	default 3
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select GENERIC_RISCV
+	select RISCV_PRIV_1_9_1
+	imply DM_SERIAL
+	imply SIFIVE_SERIAL
+	imply SIFIVE_CLINT
+	imply POWER_DOMAIN
+	imply SIMPLE_PM_BUS
+	imply CLK_CCF
+	imply CLK_COMPOSITE_CCF
+	imply CLK_K210
+	imply DM_RESET
+	imply RESET_SYSCON
+	imply SYSRESET
+	imply SYSRESET_SYSCON
+	imply SPI
+	imply DESIGNWARE_SPI
+	imply SPI_FLASH_WINBOND
+	imply MMC
+	imply MMC_SPI
+	imply MMC_BROKEN_CD
+	imply CMD_MMC
+endif
diff --git a/board/sipeed/maix/MAINTAINERS b/board/sipeed/maix/MAINTAINERS
new file mode 100644
index 0000000000..1f33882e1e
--- /dev/null
+++ b/board/sipeed/maix/MAINTAINERS
@@ -0,0 +1,11 @@ 
+Sipeed Maix BOARD
+M:	Sean Anderson <seanga2 at gmail.com>
+S:	Maintained
+F:	arch/riscv/dts/k210.dtsi
+F:	arch/riscv/dts/k210-maix-bit.dts
+F:	board/sipeed/maix/
+F:	configs/sipeed_maix_defconfig
+F:	doc/board/sipeed/
+F:	include/configs/sipeed-maix.h
+F:	include/dt-bindings/*/k210-sysctl.h
+F:	test/dm/k210_pll.c
diff --git a/board/sipeed/maix/Makefile b/board/sipeed/maix/Makefile
new file mode 100644
index 0000000000..4acff5b31e
--- /dev/null
+++ b/board/sipeed/maix/Makefile
@@ -0,0 +1,5 @@ 
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2019 Western Digital Corporation or its affiliates.
+
+obj-y += maix.o
diff --git a/board/sipeed/maix/maix.c b/board/sipeed/maix/maix.c
new file mode 100644
index 0000000000..f8e773acf7
--- /dev/null
+++ b/board/sipeed/maix/maix.c
@@ -0,0 +1,9 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Sean Anderson <seanga2 at gmail.com>
+ */
+
+int board_init(void)
+{
+	return 0;
+}
diff --git a/configs/sipeed_maix_bitm_defconfig b/configs/sipeed_maix_bitm_defconfig
new file mode 100644
index 0000000000..22d814ec7f
--- /dev/null
+++ b/configs/sipeed_maix_bitm_defconfig
@@ -0,0 +1,10 @@ 
+CONFIG_RISCV=y
+CONFIG_TARGET_SIPEED_MAIX=y
+CONFIG_ARCH_RV64I=y
+# CONFIG_LEGACY_IMAGE_FORMAT is not set
+# CONFIG_AUTOBOOT is not set
+# CONFIG_NET is not set
+# CONFIG_INPUT is not set
+# CONFIG_MTD is not set
+# CONFIG_DM_ETH is not set
+# CONFIG_EFI_LOADER is not set
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 00e72f57cd..1b3abc82f5 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -15,4 +15,5 @@  Board-specific doc
    intel/index
    renesas/index
    sifive/index
+   sipeed/index
    xilinx/index
diff --git a/doc/board/sipeed/index.rst b/doc/board/sipeed/index.rst
new file mode 100644
index 0000000000..92da47fddd
--- /dev/null
+++ b/doc/board/sipeed/index.rst
@@ -0,0 +1,9 @@ 
+.. SPDX-License-Identifier: GPL-2.0+
+
+Kendryte
+========
+
+.. toctree::
+   :maxdepth: 2
+
+   maix
diff --git a/doc/board/sipeed/maix.rst b/doc/board/sipeed/maix.rst
new file mode 100644
index 0000000000..d31da05f73
--- /dev/null
+++ b/doc/board/sipeed/maix.rst
@@ -0,0 +1,94 @@ 
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2020 Sean Anderson <seanga2 at gmail.com>
+
+Maix Bit
+========
+
+Several of the Sipeed Maix series of boards cotain the Kendryte K210 processor,
+a 64-bit RISC-V CPU. This processor contains several peripherals to accelerate
+neural network processing and other "ai" tasks. This includes a "KPU" neural
+network processor, an audio processor supporting beamforming reception, and a
+digital video port supporting capture and output at VGA resolution. Other
+peripherals include 8M of SRAM (accessible with and without caching); remappable
+pins, including 40 GPIOs; AES, FFT, and SHA256 accelerators; a DMA controller;
+and I2C, I2S, and SPI controllers. Maix peripherals vary, but include spi flash;
+on-board usb-serial bridges; ports for cameras, displays, and sd cards; and
+ESP32 chips. Currently, only the Sipeed Maix Bit V2.0 (bitm) is supported, but
+the boards are fairly similar.
+
+Documentation for Maix boards is available from
+`Sipeed's website <http://dl.sipeed.com/MAIX/HDK/>`_.
+Documentation for the Kendryte K210 is available from
+`Kendryte's website <https://kendryte.com/downloads/>`_. However, hardware
+details are rather lacking, so most technical reference has been taken from the
+`standalone sdk <https://github.com/kendryte/kendryte-standalone-sdk>`_.
+
+Build and boot steps
+--------------------
+
+To build u-boot, run
+
+.. code-block:: none
+
+    make sipeed_maix_bitm_defconfig
+    make CROSS_COMPILE=<your cross compile prefix>
+
+To flash u-boot to a maix bit, run
+
+.. code-block:: none
+
+    kflash -tp /dev/<your tty here> -B bit_mic u-boot-dtb.bin
+
+Boot output should look like the following:
+
+.. code-block:: none
+
+    
+    U-Boot 2020.01-00465-g1da52c6c9a (Feb 10 2020 - 20:26:50 -0500)
+    
+    DRAM:  8 MiB
+    MMC:
+    In:    serial at 38000000
+    Out:   serial at 38000000
+    Err:   serial at 38000000
+    =>
+
+To boot a payload, first flash it to the board. This can be done by passing the
+``-a <ADDRESS>`` option to kflash. After flashing your payload, load it by
+running
+
+.. code-block:: none
+
+    => sf probe
+    SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB
+    => sf read 80000000 <ADDRESS + 5> <SIZE>
+    device 0 offset <ADDRESS + 5>, size <SIZE>
+    SF: <SIZE> bytes @ <ADDRESS + 5> Read: OK
+    => go 80000000
+    ## Starting application at 0x80000000 ...
+
+**NB:** kflash adds a 5-byte header to payloads (and a 32-byte trailer) to all
+payloads it flashes. To load your payload properly, you will need to add 5 bytes
+to the address that you gave to kflash.
+
+The MMC (SD-card reader) does not work yet.
+
+Over- and Under-clocking
+------------------------
+
+To change the clock speed of the K210, you will need to enable
+``CONFIG_CLK_K210_SET_RATE`` and edit the board's device tree. To do this, add a
+section to ``arch/riscv/arch/riscv/dts/k210-maix-bit.dts`` like the following:
+
+.. code-block:: dts
+
+    &sysclk {
+ 	assigned-clocks = <&sysclk K210_CLK_PLL0>;
+ 	assigned-clock-rates = <780000000>;
+    };
+
+There are three PLLs on the K210: PLL0 is the parent of most of the components,
+including the CPU and RAM. PLL1 is the parent of the neural network coprocessor.
+PLL2 is the parent of the sound processing devices. Note that child clocks of
+PLL0 and PLL2 run at *half* the speed of the PLLs. For example, if PLL0 is
+running at 800 MHz, then the CPU will run at 400 MHz.
diff --git a/include/configs/sipeed-maix.h b/include/configs/sipeed-maix.h
new file mode 100644
index 0000000000..ee69a6f22e
--- /dev/null
+++ b/include/configs/sipeed-maix.h
@@ -0,0 +1,17 @@ 
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019-20 Sean Anderson <seanga2 at gmail.com>
+ */
+
+#ifndef CONFIGS_SIPEED_MAIX_H
+#define CONFIGS_SIPEED_MAIX_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_LOAD_ADDR 0x80000000
+/* Start just below the second bank */
+#define CONFIG_SYS_INIT_SP_ADDR 0x803FFFFF
+#define CONFIG_SYS_MALLOC_LEN SZ_8K
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
+#endif /* CONFIGS_SIPEED_MAIX_H */