From patchwork Thu Apr 2 11:41:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 237108 List-Id: U-Boot discussion From: jagan at amarulasolutions.com (Jagan Teki) Date: Thu, 2 Apr 2020 17:11:21 +0530 Subject: [PATCH v3 1/5] clk: rk3399: Set empty for vopl assigned-clocks In-Reply-To: <20200402114125.2501-1-jagan@amarulasolutions.com> References: <20200402114125.2501-1-jagan@amarulasolutions.com> Message-ID: <20200402114125.2501-2-jagan@amarulasolutions.com> During vidconsole probe, the device probe will try to check whether the assigned clocks on that video console node is initialized or not? and return an error if not. But, unlike Linux U-Boot won't require to handle these vopl assigned-clocks since core clocks are enough to handle the video out to process. So, mark them as empty in set_rate to satisfy clk_set_defaults so-that probe happened properly. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- Changes for v3: - new patch drivers/clk/rockchip/clk_rk3399.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 865b80cc0f..1f62376595 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -994,6 +994,13 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) case DCLK_VOP1: ret = rk3399_vop_set_clk(priv->cru, clk->id, rate); break; + case ACLK_VOP1: + case HCLK_VOP1: + /** + * assigned-clocks handling won't require for vopl, so + * return 0 to satisfy clk_set_defaults during device probe. + */ + return 0; case SCLK_DDRCLK: ret = rk3399_ddr_set_clk(priv->cru, rate); break;