From patchwork Sat Apr 25 11:03:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 238466 List-Id: U-Boot discussion From: jagan at amarulasolutions.com (Jagan Teki) Date: Sat, 25 Apr 2020 16:33:49 +0530 Subject: [PATCH 3/8] clk: rk3399: Enable PCIE_PHY clock In-Reply-To: <20200425110354.12381-1-jagan@amarulasolutions.com> References: <20200425110354.12381-1-jagan@amarulasolutions.com> Message-ID: <20200425110354.12381-4-jagan@amarulasolutions.com> Add PCIE_PHY clock enablement support on rk3399 clock driver. This clock is enabled by default, so do nothing if it triggers during the PCIe PHY probe other PHY users on this clock will simply fail. Signed-off-by: Jagan Teki --- drivers/clk/rockchip/clk_rk3399.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index d822acace1..8e069fbade 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1071,12 +1071,27 @@ static int __maybe_unused rk3399_clk_set_parent(struct clk *clk, return -ENOENT; } +static int rk3399_clk_enable(struct clk *clk) +{ + switch (clk->id) { + case SCLK_PCIEPHY_REF: + /* do nothing, clk is enabled by default */ + break; + default: + debug("%s: unsupported clk %ld\n", __func__, clk->id); + return -ENOENT; + } + + return 0; +} + static struct clk_ops rk3399_clk_ops = { .get_rate = rk3399_clk_get_rate, .set_rate = rk3399_clk_set_rate, #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) .set_parent = rk3399_clk_set_parent, #endif + .enable = rk3399_clk_enable, }; #ifdef CONFIG_SPL_BUILD