From patchwork Sat May 2 08:59:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 244774 List-Id: U-Boot discussion From: sr at denx.de (Stefan Roese) Date: Sat, 2 May 2020 10:59:43 +0200 Subject: [PATCH v1 09/10] mips: octeon: dts: Add Octeon 3 cn73xx base dtsi file In-Reply-To: <20200502085944.13444-1-sr@denx.de> References: <20200502085944.13444-1-sr@denx.de> Message-ID: <20200502085944.13444-10-sr@denx.de> This patch adds the base dtsi file for the Octeon 3 cn73xx SoC. Signed-off-by: Stefan Roese --- MAINTAINERS | 1 + arch/mips/dts/mrvl,cn73xx.dtsi | 64 ++++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) create mode 100644 arch/mips/dts/mrvl,cn73xx.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index 29f2d7328c..71d257c214 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -754,6 +754,7 @@ M: Aaron Williams S: Maintained F: arch/mips/mach-octeon/ F: arch/mips/include/asm/arch-octeon/ +F: arch/mips/dts/mrvl,cn73xx.dtsi MMC M: Peng Fan diff --git a/arch/mips/dts/mrvl,cn73xx.dtsi b/arch/mips/dts/mrvl,cn73xx.dtsi new file mode 100644 index 0000000000..90872a3b4b --- /dev/null +++ b/arch/mips/dts/mrvl,cn73xx.dtsi @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Marvell / Cavium Inc. CN73xx + */ + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + + soc at 0 { + interrupt-parent = <&ciu3>; + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; /* Direct mapping */ + + ciu3: interrupt-controller at 1010000000000 { + compatible = "cavium,octeon-7890-ciu3"; + interrupt-controller; + /* + * Interrupts are specified by two parts: + * 1) Source number (20 significant bits) + * 2) Trigger type: (4 == level, 1 == edge) + */ + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x10100 0x00000000 0x0 0xb0000000>; + }; + + bootbus: bootbus at 1180000000000 { + compatible = "cavium,octeon-3860-bootbus","simple-bus"; + reg = <0x11800 0x00000000 0x0 0x200>; + /* The chip select number and offset */ + #address-cells = <2>; + /* The size of the chip select region */ + #size-cells = <1>; + }; + + reset: reset at 1180006001600 { + compatible = "mrvl,cn7xxx-rst"; + reg = <0x11800 0x06001600 0x0 0x200>; + }; + + uart0: serial at 1180000000800 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000800 0x0 0x400>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <0x08000 4>; + }; + + uart1: serial at 1180000000c00 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000c00 0x0 0x400>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <0x08040 4>; + }; + }; +};