From patchwork Sat May 2 08:59:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 244766 List-Id: U-Boot discussion From: sr at denx.de (Stefan Roese) Date: Sat, 2 May 2020 10:59:36 +0200 Subject: [PATCH v1 02/10] mips: cache: Allow using CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM In-Reply-To: <20200502085944.13444-1-sr@denx.de> References: <20200502085944.13444-1-sr@denx.de> Message-ID: <20200502085944.13444-3-sr@denx.de> This patch enables the usage of CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM, which is what is needed for the newly added Octeon platform. Signed-off-by: Stefan Roese --- arch/mips/lib/cache.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c index 1a8c87d094..9e20b39608 100644 --- a/arch/mips/lib/cache.c +++ b/arch/mips/lib/cache.c @@ -7,7 +7,7 @@ #include #include #include -#ifdef CONFIG_MIPS_L2_CACHE +#ifdef CONFIG_MIPS_CM #include #endif #include @@ -16,6 +16,17 @@ DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_MIPS_L2_CACHE) && !defined(CONFIG_MIPS_CM) +/* + * Dummy implementation to avoid compile warning on platforms with L2 + * cache but without CM + */ +static unsigned long mips_cm_l2_line_size(void) +{ + return 0; +} +#endif + static void probe_l2(void) { #ifdef CONFIG_MIPS_L2_CACHE