diff mbox series

[v7,08/22] riscv: sifive: dts: fu540: add U-Boot dmc node

Message ID	20200502100628.24809-9-pragnesh.patel@sifive.com
State	Superseded
Headers	show List-Id: U-Boot discussion <u-boot.lists.denx.de> From: pragnesh.patel at sifive.com (Pragnesh Patel) Date: Sat, 2 May 2020 15:36:12 +0530 Subject: [PATCH v7 08/22] riscv: sifive: dts: fu540: add U-Boot dmc node In-Reply-To: <20200502100628.24809-1-pragnesh.patel@sifive.com> References: <20200502100628.24809-1-pragnesh.patel@sifive.com> Message-ID: <20200502100628.24809-9-pragnesh.patel@sifive.com>
Series	RISC-V SiFive FU540 support SPL \| expand [v7,00/22] RISC-V SiFive FU540 support SPL [v7,01/22] misc: add driver for the SiFive otp controller [v7,02/22] riscv: sifive: fu540: Use OTP DM driver for serial environment variable [v7,03/22] riscv: Add _image_binary_end for SPL [v7,04/22] lib: Makefile: build crc7.c when CONFIG_MMC_SPI [v7,05/22] riscv: sifive: dts: fu540: Add board -u-boot.dtsi files [v7,06/22] sifive: fu540: add ddr driver [v7,07/22] sifive: dts: fu540: Add DDR controller and phy register settings [v7,08/22] riscv: sifive: dts: fu540: add U-Boot dmc node [v7,09/22] clk: sifive: fu540-prci: Add clock enable and disable ops [v7,10/22] clk: sifive: fu540-prci: ddr and ethernet clock initialization in SPL [v7,11/22] riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux [v7,12/22] sifive: dts: fu540: Enable gpio in U-Boot SPL [v7,13/22] riscv: cpu: fu540: Add support for cpu fu540 [v7,14/22] riscv: Add place-holder for driver compilation [v7,15/22] riscv: sifive: dts: fu540: Add clock for cpus node [v7,16/22] riscv: Enable cpu clock if it is present [v7,17/22] riscv: sifive: fu540: add SPL configuration [v7,18/22] configs: fu540: Add config options for U-Boot SPL [v7,19/22] sifive: dts: fu540: Enable L2 Cache in U-Boot [v7,20/22] riscv: sifive: fu540: enable all cache ways from U-Boot proper [v7,21/22] doc: sifive: fu540: Add description for OpenSBI generic platform [v7,22/22] doc: sifive: fu540: Add description for RISC-V FU540 U-Boot SPL

Commit Message

Pragnesh Patel May 2, 2020, 10:06 a.m. UTC

Add dmc node to enable sdram driver. dmc is used to
initialize the memory controller.

Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com>
---
 arch/riscv/dts/fu540-c000-u-boot.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

Comments

Bin Meng May 2, 2020, 12:29 p.m. UTC | #1

On Sat, May 2, 2020 at 6:08 PM Pragnesh Patel <pragnesh.patel at sifive.com> wrote:
>
> Add dmc node to enable sdram driver. dmc is used to
> initialize the memory controller.
>
> Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com>
> ---
>  arch/riscv/dts/fu540-c000-u-boot.dtsi | 9 +++++++++
>  1 file changed, 9 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
Tested-by: Bin Meng <bmeng.cn at gmail.com>

diff mbox series

Patch

diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index 387b13bdfb..e93b8a9bcf 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -52,6 +52,15 @@ 
 			reg = <0x0 0x2000000 0x0 0xc0000>;
 			u-boot,dm-spl;
 		};
+		dmc: dmc at 100b0000 {
+			compatible = "sifive,fu540-c000-ddr";
+			reg = <0x0 0x100b0000 0x0 0x0800
+			       0x0 0x100b2000 0x0 0x2000
+			       0x0 0x100b8000 0x0 0x0fff>;
+			clocks = <&prci PRCI_CLK_DDRPLL>;
+			clock-frequency = <933333324>;
+			u-boot,dm-spl;
+		};
 	};
 };