From patchwork Mon May 4 11:44:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rayagonda Kokatanur X-Patchwork-Id: 244990 List-Id: U-Boot discussion From: rayagonda.kokatanur at broadcom.com (Rayagonda Kokatanur) Date: Mon, 4 May 2020 17:14:29 +0530 Subject: [PATCH v2 13/16] board: ns3: limit U-boot relocation within 16MB memory In-Reply-To: <20200504114432.10886-1-rayagonda.kokatanur@broadcom.com> References: <20200504114432.10886-1-rayagonda.kokatanur@broadcom.com> Message-ID: <20200504114432.10886-14-rayagonda.kokatanur@broadcom.com> From: Bharat Kumar Reddy Gooty By default re-location happens to higher address of DDR, i.e, DDR start + DDR size. Limit re-location to happen within 16MB memory, start 0xFF00_0000 and end 0x1_0000_0000 Signed-off-by: Bharat Kumar Reddy Gooty Signed-off-by: Rayagonda Kokatanur --- board/broadcom/bcmns3/ns3.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c index 514c2050b2..51cab1aad3 100644 --- a/board/broadcom/bcmns3/ns3.c +++ b/board/broadcom/bcmns3/ns3.c @@ -121,6 +121,11 @@ static void mem_info_parse_fixup(void *fdt) int board_init(void) { + /* Setup memory using "memory" node from DTB */ + if (fdtdec_setup_mem_size_base() != 0) + return -EINVAL; + fdtdec_setup_memory_banksize(); + if (bl33_info->version != BL33_INFO_VERSION) printf("*** warning: ATF BL31 and u-boot not in sync! ***\n"); @@ -134,19 +139,30 @@ int board_late_init(void) int dram_init(void) { - if (fdtdec_setup_mem_size_base() != 0) - return -EINVAL; + /* + * Mark ram base as the last 16MB of 2GB DDR, which is 0xFF00_0000. + * So that relocation happens with in the last 16MB memory. + */ + gd->ram_base = (phys_size_t)(BCM_NS3_MEM_END - SZ_16M); + gd->ram_size = (unsigned long)SZ_16M; return 0; } int dram_init_banksize(void) { - fdtdec_setup_memory_banksize(); + gd->bd->bi_dram[0].start = (BCM_NS3_MEM_END - SZ_16M); + gd->bd->bi_dram[0].size = SZ_16M; return 0; } +/* Limit RAM used by U-Boot to the DDR first bank End region */ +ulong board_get_usable_ram_top(ulong total_size) +{ + return BCM_NS3_MEM_END; +} + void reset_cpu(ulong level) { #define L3_RESET 30