From patchwork Wed May 6 07:50:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 245170 List-Id: U-Boot discussion From: jagan at amarulasolutions.com (Jagan Teki) Date: Wed, 6 May 2020 13:20:20 +0530 Subject: [PATCH v2 2/7] clk: rk3399: Set empty for TCPHY assigned-clocks In-Reply-To: <20200506075025.1677-1-jagan@amarulasolutions.com> References: <20200506075025.1677-1-jagan@amarulasolutions.com> Message-ID: <20200506075025.1677-3-jagan@amarulasolutions.com> Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi have SCLK_UPHY0_TCPDCORE, SCLK_UPHY1_TCPDCORE assigned-clocks which are usually required for Linux and don't require to handle them in U-Boot. assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; So, mark them as empty in clock otherwise device probe on those typec phy driver would fail. Signed-off-by: Jagan Teki --- Changes for v2: - new patch drivers/clk/rockchip/clk_rk3399.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index b1c89ea127..4d48f70685 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -997,6 +997,8 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) case ACLK_VOP1: case HCLK_VOP1: case HCLK_SD: + case SCLK_UPHY0_TCPDCORE: + case SCLK_UPHY1_TCPDCORE: /** * assigned-clocks handling won't require for vopl, so * return 0 to satisfy clk_set_defaults during device probe.