diff mbox series

[RFC,1/2] arm: provide a function for boards init code to modify MMU virtual-physical map

Message ID 20200512131746.22797-2-m.szyprowski@samsung.com
State New
Headers show
Series ARM: arbitrary virtual-physical mappings for RPi4 XHCI support | expand

Commit Message

Marek Szyprowski May 12, 2020, 1:17 p.m. UTC
Provide a function for setting arbitrary virtual-physical MMU mapping
for the given region.

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
---
 arch/arm/include/asm/mmu.h    |  8 ++++++++
 arch/arm/include/asm/system.h | 18 ++++++++++++++++--
 arch/arm/lib/cache-cp15.c     | 18 ++++++++++++------
 3 files changed, 36 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/include/asm/mmu.h

Comments

Sylwester Nawrocki May 12, 2020, 3:11 p.m. UTC | #1
On 12.05.2020 15:17, Marek Szyprowski wrote:
> -void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
> -				     enum dcache_option option);
> +static inline void mmu_set_region_dcache_behaviour(phys_addr_t start,
> +			size_t size, enum dcache_option option)

aarch64 build fails with an error:

arch/arm/cpu/armv8/cache_v8.c:555:6: error: redefinition of ?mmu_set_region_dcache_behaviour?
 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from ./arch/arm/include/asm/cache.h:11:0,
                 from include/net.h:15,
                 from include/common.h:41,
                 from arch/arm/cpu/armv8/cache_v8.c:10:
./arch/arm/include/asm/system.h:593:20: note: previous definition of ?mmu_set_region_dcache_behaviour? was here
 static inline void mmu_set_region_dcache_behaviour(phys_addr_t start,
                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  CC      common/exports.o
scripts/Makefile.build:265: recipe for target 'arch/arm/cpu/armv8/cache_v8.o' failed
make[1]: *** [arch/arm/cpu/armv8/cache_v8.o] Error 1
Makefile:1790: recipe for target 'arch/arm/cpu/armv8' failed
make: *** [arch/arm/cpu/armv8] Error 2
diff mbox series

Patch

diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
new file mode 100644
index 0000000..fe3d793
--- /dev/null
+++ b/arch/arm/include/asm/mmu.h
@@ -0,0 +1,8 @@ 
+#ifndef __ASM_ARM_MMU_H
+#define __ASM_ARM_MMU_H
+
+#ifdef CONFIG_ADDR_MAP
+extern void init_addr_map(void);
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 81ccead..a513f4a 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -573,14 +573,28 @@  s32 psci_features(u32 function_id, u32 psci_fid);
 void save_boot_params_ret(void);
 
 /**
+ * Change the virt/phys mapping and cache settings for a region.
+ *
+ * \param virt		virtual start address of memory region to change
+ * \param phys		physical address for the memory region to set
+ * \param size		size of memory region to change
+ * \param option	dcache option to select
+ */
+void mmu_set_region_dcache_behaviour_phys(phys_addr_t virt, phys_addr_t phys,
+					size_t size, enum dcache_option option);
+
+/**
  * Change the cache settings for a region.
  *
  * \param start		start address of memory region to change
  * \param size		size of memory region to change
  * \param option	dcache option to select
  */
-void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
-				     enum dcache_option option);
+static inline void mmu_set_region_dcache_behaviour(phys_addr_t start,
+			size_t size, enum dcache_option option)
+{
+	mmu_set_region_dcache_behaviour_phys(start, start, size, option);
+}
 
 #ifdef CONFIG_SYS_NONCACHED_MEMORY
 void noncached_init(void);
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index f8d2096..7c14d1d 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -24,7 +24,8 @@  __weak void arm_init_domains(void)
 {
 }
 
-void set_section_dcache(int section, enum dcache_option option)
+static void set_section_phys(int section, phys_addr_t phys,
+			     enum dcache_option option)
 {
 #ifdef CONFIG_ARMV7_LPAE
 	u64 *page_table = (u64 *)gd->arch.tlb_addr;
@@ -36,7 +37,7 @@  void set_section_dcache(int section, enum dcache_option option)
 #endif
 
 	/* Add the page offset */
-	value |= ((u32)section << MMU_SECTION_SHIFT);
+	value |= phys;
 
 	/* Add caching bits */
 	value |= option;
@@ -45,13 +46,18 @@  void set_section_dcache(int section, enum dcache_option option)
 	page_table[section] = value;
 }
 
+void set_section_dcache(int section, enum dcache_option option)
+{
+	set_section_phys(section, (u32)section << MMU_SECTION_SHIFT, option);
+}
+
 __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
 {
 	debug("%s: Warning: not implemented\n", __func__);
 }
 
-void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
-				     enum dcache_option option)
+void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys,
+					size_t size, enum dcache_option option)
 {
 #ifdef CONFIG_ARMV7_LPAE
 	u64 *page_table = (u64 *)gd->arch.tlb_addr;
@@ -70,8 +76,8 @@  void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 	debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
 	      option);
 #endif
-	for (upto = start; upto < end; upto++)
-		set_section_dcache(upto, option);
+	for (upto = start; upto < end; upto++, phys += MMU_SECTION_SIZE)
+		set_section_phys(upto, phys, option);
 
 	/*
 	 * Make sure range is cache line aligned