From patchwork Thu May 14 09:59:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 245769 List-Id: U-Boot discussion From: sr at denx.de (Stefan Roese) Date: Thu, 14 May 2020 11:59:03 +0200 Subject: [PATCH v2 03/12] mips: cache: Allow using CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM In-Reply-To: <20200514095912.14428-1-sr@denx.de> References: <20200514095912.14428-1-sr@denx.de> Message-ID: <20200514095912.14428-4-sr@denx.de> This patch enables the usage of CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM, which is what is needed for the newly added Octeon platform. Signed-off-by: Stefan Roese --- Changes in v2: - Restructure patch by adding empty functions to asm/cm.h instead arch/mips/include/asm/cm.h | 12 ++++++++++++ arch/mips/lib/cache.c | 2 -- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/cm.h b/arch/mips/include/asm/cm.h index 8f37471f81..06d721d228 100644 --- a/arch/mips/include/asm/cm.h +++ b/arch/mips/include/asm/cm.h @@ -40,6 +40,7 @@ #include +#if CONFIG_IS_ENABLED(MIPS_CM) static inline void *mips_cm_base(void) { return (void *)CKSEG1ADDR(CONFIG_MIPS_CM_BASE); @@ -55,6 +56,17 @@ static inline unsigned long mips_cm_l2_line_size(void) line_sz &= GENMASK(GCR_L2_CONFIG_LINESZ_BITS - 1, 0); return line_sz ? (2 << line_sz) : 0; } +#else +static inline void *mips_cm_base(void) +{ + return NULL; +} + +static inline unsigned long mips_cm_l2_line_size(void) +{ + return 0; +} +#endif #endif /* !__ASSEMBLY__ */ diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c index 1a8c87d094..fdffe9493b 100644 --- a/arch/mips/lib/cache.c +++ b/arch/mips/lib/cache.c @@ -7,9 +7,7 @@ #include #include #include -#ifdef CONFIG_MIPS_L2_CACHE #include -#endif #include #include #include