diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 6816acdf4f..de5753333b 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -458,11 +458,6 @@ config TARGET_OPOS6ULDEV
 	bool "Armadeus OPOS6ULDev board"
 	select MX6UL_OPOS6UL
 
-config TARGET_OT1200
-	bool "Bachmann OT1200"
-	select SUPPORT_SPL
-	imply CMD_SATA
-
 config TARGET_PICO_IMX6
 	bool "PICO-IMX6"
 	select BOARD_EARLY_INIT_F
@@ -649,7 +644,6 @@ source "board/ge/bx50v3/Kconfig"
 source "board/advantech/dms-ba16/Kconfig"
 source "board/aristainetos/Kconfig"
 source "board/armadeus/opos6uldev/Kconfig"
-source "board/bachmann/ot1200/Kconfig"
 source "board/barco/platinum/Kconfig"
 source "board/barco/titanium/Kconfig"
 source "board/boundary/nitrogen6x/Kconfig"
diff --git a/board/bachmann/ot1200/Kconfig b/board/bachmann/ot1200/Kconfig
deleted file mode 100644
index 4ccb60a97f..0000000000
--- a/board/bachmann/ot1200/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_OT1200
-
-config SYS_BOARD
-	default "ot1200"
-
-config SYS_VENDOR
-	default "bachmann"
-
-config SYS_CONFIG_NAME
-	default "ot1200"
-
-endif
diff --git a/board/bachmann/ot1200/MAINTAINERS b/board/bachmann/ot1200/MAINTAINERS
deleted file mode 100644
index ad75c24ee4..0000000000
--- a/board/bachmann/ot1200/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BACHMANN ELECTRONIC OT1200 BOARD
-M:	Christian Gmeiner <christian.gmeiner at gmail.com>
-S:	Maintained
-F:	board/bachmann/ot1200
-F:	include/configs/ot1200.h
-F:	configs/ot1200*_defconfig
diff --git a/board/bachmann/ot1200/Makefile b/board/bachmann/ot1200/Makefile
deleted file mode 100644
index 73000e3d3c..0000000000
--- a/board/bachmann/ot1200/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2012-2013, Guennadi Liakhovetski <lg at denx.de>
-# (C) Copyright 2012-2013 Freescale Semiconductor, Inc.
-# Copyright (C) 2013, Boundary Devices <info at boundarydevices.com>
-
-ifdef CONFIG_SPL_BUILD
-obj-y  := ot1200.o ot1200_spl.o
-else
-obj-y  := ot1200.o
-endif
diff --git a/board/bachmann/ot1200/README b/board/bachmann/ot1200/README
deleted file mode 100644
index c03d44e458..0000000000
--- a/board/bachmann/ot1200/README
+++ /dev/null
@@ -1,20 +0,0 @@
-U-Boot for the Bachmann electronic GmbH OT1200 devices
-
-There are two different versions of the base board, which differ
-in the way ethernet is done. The variant detection is done during
-runtime based on the address of the found phy.
-
-- "mr" variant
-FEC is connected directly to an ethernet switch (KSZ8895). The ethernet
-port is always up and auto-negotiation is not possible.
-
-- normal variant
-FEC is connected to a normal phy and auto-negotiation is possible.
-
-
-The variant name is part of the dtb file name loaded by u-boot. This
-make is possible to boot the linux kernel and make use variant specific
-devicetree (fixed-phy link).
-
-In order to support different display resoltuions/sizes the OT1200 devices
-are making use of EDID data stored in an i2c EEPROM.
diff --git a/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg b/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg
deleted file mode 100644
index f4f605fc8d..0000000000
--- a/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg
+++ /dev/null
@@ -1,154 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc.
- * Jason Liu <r64343 at freescale.com>
- *
- * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM      sd
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type           Address        Value
- *
- * where:
- *      Addr-type register length (1,2 or 4 bytes)
- *      Address   absolute address of the register
- *      value     value to be stored in the register
- */
-DATA 4 0x020e05a8 0x00000030
-DATA 4 0x020e05b0 0x00000030
-DATA 4 0x020e0524 0x00000030
-DATA 4 0x020e051c 0x00000030
-
-DATA 4 0x020e0518 0x00000030
-DATA 4 0x020e050c 0x00000030
-DATA 4 0x020e05b8 0x00000030
-DATA 4 0x020e05c0 0x00000030
-
-DATA 4 0x020e05ac 0x00020030
-DATA 4 0x020e05b4 0x00020030
-DATA 4 0x020e0528 0x00020030
-DATA 4 0x020e0520 0x00020030
-
-DATA 4 0x020e0514 0x00020030
-DATA 4 0x020e0510 0x00020030
-DATA 4 0x020e05bc 0x00020030
-DATA 4 0x020e05c4 0x00020030
-
-DATA 4 0x020e056c 0x00020030
-DATA 4 0x020e0578 0x00020030
-DATA 4 0x020e0588 0x00020030
-DATA 4 0x020e0594 0x00020030
-
-DATA 4 0x020e057c 0x00020030
-DATA 4 0x020e0590 0x00003000
-DATA 4 0x020e0598 0x00003000
-DATA 4 0x020e058c 0x00000000
-
-DATA 4 0x020e059c 0x00003030
-DATA 4 0x020e05a0 0x00003030
-DATA 4 0x020e0784 0x00000030
-DATA 4 0x020e0788 0x00000030
-
-DATA 4 0x020e0794 0x00000030
-DATA 4 0x020e079c 0x00000030
-DATA 4 0x020e07a0 0x00000030
-DATA 4 0x020e07a4 0x00000030
-
-DATA 4 0x020e07a8 0x00000030
-DATA 4 0x020e0748 0x00000030
-DATA 4 0x020e074c 0x00000030
-DATA 4 0x020e0750 0x00020000
-
-DATA 4 0x020e0758 0x00000000
-DATA 4 0x020e0774 0x00020000
-DATA 4 0x020e078c 0x00000030
-DATA 4 0x020e0798 0x000C0000
-
-DATA 4 0x021b081c 0x33333333
-DATA 4 0x021b0820 0x33333333
-DATA 4 0x021b0824 0x33333333
-DATA 4 0x021b0828 0x33333333
-
-DATA 4 0x021b481c 0x33333333
-DATA 4 0x021b4820 0x33333333
-DATA 4 0x021b4824 0x33333333
-DATA 4 0x021b4828 0x33333333
-
-DATA 4 0x021b0018 0x00081740
-
-DATA 4 0x021b001c 0x00008000
-DATA 4 0x021b000c 0x555A7974
-DATA 4 0x021b0010 0xDB538F64
-DATA 4 0x021b0014 0x01FF00DB
-DATA 4 0x021b002c 0x000026D2
-
-DATA 4 0x021b0030 0x005A1023
-DATA 4 0x021b0008 0x09444040
-DATA 4 0x021b0004 0x00025576
-DATA 4 0x021b0040 0x00000027
-DATA 4 0x021b0000 0x831A0000
-
-DATA 4 0x021b001c 0x04088032
-DATA 4 0x021b001c 0x0408803A
-DATA 4 0x021b001c 0x00008033
-DATA 4 0x021b001c 0x0000803B
-DATA 4 0x021b001c 0x00428031
-DATA 4 0x021b001c 0x00428039
-DATA 4 0x021b001c 0x19308030
-DATA 4 0x021b001c 0x19308038
-
-DATA 4 0x021b001c 0x04008040
-DATA 4 0x021b001c 0x04008048
-DATA 4 0x021b0800 0xA1380003
-DATA 4 0x021b4800 0xA1380003
-DATA 4 0x021b0020 0x00005800
-DATA 4 0x021b0818 0x00022227
-DATA 4 0x021b4818 0x00022227
-
-DATA 4 0x021b083c 0x434B0350
-DATA 4 0x021b0840 0x034C0359
-DATA 4 0x021b483c 0x434B0350
-DATA 4 0x021b4840 0x03650348
-DATA 4 0x021b0848 0x4436383B
-DATA 4 0x021b4848 0x39393341
-DATA 4 0x021b0850 0x35373933
-DATA 4 0x021b4850 0x48254A36
-
-DATA 4 0x021b080c 0x001F001F
-DATA 4 0x021b0810 0x001F001F
-
-DATA 4 0x021b480c 0x00440044
-DATA 4 0x021b4810 0x00440044
-
-DATA 4 0x021b08b8 0x00000800
-DATA 4 0x021b48b8 0x00000800
-
-DATA 4 0x021b001c 0x00000000
-DATA 4 0x021b0404 0x00011006
-
-
-/*
- * Setup CCM_CCOSR register as follows:
- *
- * cko1_en  = 1	   --> CKO1 enabled
- * cko1_div = 111  --> divide by 8
- * cko1_sel = 1011 --> ahb_clk_root
- *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
- */
-DATA 4 0x020c4060 0x000000fb
diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c
deleted file mode 100644
index db0da0ca2f..0000000000
--- a/board/bachmann/ot1200/ot1200.c
+++ /dev/null
@@ -1,359 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
- * Copyright (C) 2014, Bachmann electronic GmbH
- */
-
-#include <common.h>
-#include <init.h>
-#include <net.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <env.h>
-#include <malloc.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/sata.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/sys_proto.h>
-#include <mmc.h>
-#include <fsl_esdhc_imx.h>
-#include <netdev.h>
-#include <i2c.h>
-#include <pca953x.h>
-#include <asm/gpio.h>
-#include <phy.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define OUTPUT_40OHM	(PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
-
-#define UART_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
-	OUTPUT_40OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL	(PAD_CTL_PUS_47K_UP |			\
-	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
-	PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL	(PAD_CTL_PUS_100K_UP | OUTPUT_40OHM |	\
-	PAD_CTL_HYS)
-
-#define SPI_PAD_CTRL	(PAD_CTL_HYS | OUTPUT_40OHM |		\
-	PAD_CTL_SRE_FAST)
-
-#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP | OUTPUT_40OHM |	\
-	PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-int dram_init(void)
-{
-	gd->ram_size = imx_ddr_size();
-
-	return 0;
-}
-
-static iomux_v3_cfg_t const uart1_pads[] = {
-	MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static void setup_iomux_uart(void)
-{
-	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
-}
-
-static iomux_v3_cfg_t const enet_pads[] = {
-	MX6_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-static void setup_iomux_enet(void)
-{
-	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
-}
-
-static iomux_v3_cfg_t const ecspi1_pads[] = {
-	MX6_PAD_DISP0_DAT3__ECSPI3_SS0  | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6_PAD_DISP0_DAT4__ECSPI3_SS1  | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
-};
-
-static void setup_iomux_spi(void)
-{
-	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
-}
-
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
-	return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(1, 3)) : -1;
-}
-
-static iomux_v3_cfg_t const feature_pads[] = {
-	/* SD card detect */
-	MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_DOWN),
-
-	/* eMMC soldered? */
-	MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP),
-};
-
-static void setup_iomux_features(void)
-{
-	imx_iomux_v3_setup_multiple_pads(feature_pads,
-		ARRAY_SIZE(feature_pads));
-}
-
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-/* I2C2 - EEPROM */
-static struct i2c_pads_info i2c_pad_info1 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
-		.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
-		.gp = IMX_GPIO_NR(2, 30)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
-		.gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
-		.gp = IMX_GPIO_NR(3, 16)
-	}
-};
-
-/* I2C3 - IO expander  */
-static struct i2c_pads_info i2c_pad_info2 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
-		.gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
-		.gp = IMX_GPIO_NR(3, 17)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
-		.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
-		.gp = IMX_GPIO_NR(3, 18)
-	}
-};
-
-static void setup_iomux_i2c(void)
-{
-	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
-}
-
-static void ccgr_init(void)
-{
-	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
-	writel(0x00C03F3F, &ccm->CCGR0);
-	writel(0x0030FC33, &ccm->CCGR1);
-	writel(0x0FFFC000, &ccm->CCGR2);
-	writel(0x3FF00000, &ccm->CCGR3);
-	writel(0x00FFF300, &ccm->CCGR4);
-	writel(0x0F0000C3, &ccm->CCGR5);
-	writel(0x000003FF, &ccm->CCGR6);
-}
-
-int board_early_init_f(void)
-{
-	ccgr_init();
-	gpr_init();
-
-	setup_iomux_uart();
-	setup_iomux_spi();
-	setup_iomux_i2c();
-	setup_iomux_features();
-
-	return 0;
-}
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
-	MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const usdhc4_pads[] = {
-	MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-	int ret;
-
-	if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
-		gpio_direction_input(IMX_GPIO_NR(4, 5));
-		ret = gpio_get_value(IMX_GPIO_NR(4, 5));
-	} else {
-		gpio_direction_input(IMX_GPIO_NR(1, 5));
-		ret = !gpio_get_value(IMX_GPIO_NR(1, 5));
-	}
-
-	return ret;
-}
-
-struct fsl_esdhc_cfg usdhc_cfg[2] = {
-	{USDHC3_BASE_ADDR},
-	{USDHC4_BASE_ADDR},
-};
-
-int board_mmc_init(bd_t *bis)
-{
-	int ret;
-	u32 index = 0;
-
-	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
-
-	usdhc_cfg[0].max_bus_width = 8;
-	usdhc_cfg[1].max_bus_width = 4;
-
-	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
-		switch (index) {
-		case 0:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
-			break;
-		case 1:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
-			break;
-		default:
-			printf("Warning: you configured more USDHC controllers"
-				"(%d) then supported by the board (%d)\n",
-				index + 1, CONFIG_SYS_FSL_USDHC_NUM);
-			return -EINVAL;
-		}
-
-		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-
-static void leds_on(void)
-{
-	/* turn on all possible leds connected via GPIO expander */
-	i2c_set_bus_num(2);
-	pca953x_set_dir(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, PCA953X_DIR_OUT);
-	pca953x_set_val(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, 0x0);
-}
-
-static void backlight_lcd_off(void)
-{
-	unsigned gpio = IMX_GPIO_NR(2, 0);
-	gpio_direction_output(gpio, 0);
-
-	gpio = IMX_GPIO_NR(2, 3);
-	gpio_direction_output(gpio, 0);
-}
-
-int board_eth_init(bd_t *bis)
-{
-	uint32_t base = IMX_FEC_BASE;
-	struct mii_dev *bus = NULL;
-	struct phy_device *phydev = NULL;
-	int ret;
-
-	setup_iomux_enet();
-
-	bus = fec_get_miibus(base, -1);
-	if (!bus)
-		return -EINVAL;
-
-	/* scan phy 0 and 5 */
-	phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII);
-	if (!phydev) {
-		ret = -EINVAL;
-		goto free_bus;
-	}
-
-	/* depending on the phy address we can detect our board version */
-	if (phydev->addr == 0)
-		env_set("boardver", "");
-	else
-		env_set("boardver", "mr");
-
-	printf("using phy at %d\n", phydev->addr);
-	ret = fec_probe(bis, -1, base, bus, phydev);
-	if (ret)
-		goto free_phydev;
-
-	return 0;
-
-free_phydev:
-	free(phydev);
-free_bus:
-	free(bus);
-	return ret;
-}
-
-int board_init(void)
-{
-	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
-	backlight_lcd_off();
-
-	leds_on();
-
-#ifdef CONFIG_SATA
-	setup_sata();
-#endif
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	puts("Board: "CONFIG_SYS_BOARD"\n");
-	return 0;
-}
-
-#ifdef CONFIG_CMD_BMODE
-static const struct boot_mode board_boot_modes[] = {
-	/* 4 bit bus width */
-	{"mmc0",	MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
-	{NULL,		0},
-};
-#endif
-
-int misc_init_r(void)
-{
-#ifdef CONFIG_CMD_BMODE
-	add_board_boot_modes(board_boot_modes);
-#endif
-	return 0;
-}
diff --git a/board/bachmann/ot1200/ot1200_spl.c b/board/bachmann/ot1200/ot1200_spl.c
deleted file mode 100644
index 7fbd6f2c5d..0000000000
--- a/board/bachmann/ot1200/ot1200_spl.c
+++ /dev/null
@@ -1,152 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015, Bachmann electronic GmbH
- */
-
-#include <common.h>
-#include <init.h>
-#include <spl.h>
-#include <asm/arch/mx6-ddr.h>
-
-/* Configure MX6Q/DUAL mmdc DDR io registers */
-static struct mx6dq_iomux_ddr_regs ot1200_ddr_ioregs = {
-	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 48ohm */
-	.dram_sdclk_0   = 0x00000028,
-	.dram_sdclk_1   = 0x00000028,
-	.dram_cas       = 0x00000028,
-	.dram_ras       = 0x00000028,
-	.dram_reset     = 0x00000028,
-	/* SDCKE[0:1]: 100k pull-up */
-	.dram_sdcke0    = 0x00003000,
-	.dram_sdcke1    = 0x00003000,
-	/* SDBA2: pull-up disabled */
-	.dram_sdba2	    = 0x00000000,
-	/* SDODT[0:1]: 100k pull-up, 48 ohm */
-	.dram_sdodt0    = 0x00000028,
-	.dram_sdodt1    = 0x00000028,
-	/* SDQS[0:7]: Differential input, 48 ohm */
-	.dram_sdqs0     = 0x00000028,
-	.dram_sdqs1     = 0x00000028,
-	.dram_sdqs2     = 0x00000028,
-	.dram_sdqs3     = 0x00000028,
-	.dram_sdqs4     = 0x00000028,
-	.dram_sdqs5     = 0x00000028,
-	.dram_sdqs6     = 0x00000028,
-	.dram_sdqs7     = 0x00000028,
-	/* DQM[0:7]: Differential input, 48 ohm */
-	.dram_dqm0      = 0x00000028,
-	.dram_dqm1      = 0x00000028,
-	.dram_dqm2      = 0x00000028,
-	.dram_dqm3      = 0x00000028,
-	.dram_dqm4      = 0x00000028,
-	.dram_dqm5      = 0x00000028,
-	.dram_dqm6      = 0x00000028,
-	.dram_dqm7      = 0x00000028,
-};
-
-/* Configure MX6Q/DUAL mmdc GRP io registers */
-static struct mx6dq_iomux_grp_regs ot1200_grp_ioregs = {
-	/* DDR3 */
-	.grp_ddr_type    = 0x000c0000,
-	.grp_ddrmode_ctl = 0x00020000,
-	/* Disable DDR pullups */
-	.grp_ddrpke      = 0x00000000,
-	/* ADDR[00:16], SDBA[0:1]: 48 ohm */
-	.grp_addds       = 0x00000028,
-	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 48 ohm */
-	.grp_ctlds       = 0x00000028,
-	/* DATA[00:63]: Differential input, 48 ohm */
-	.grp_ddrmode     = 0x00020000,
-	.grp_b0ds        = 0x00000028,
-	.grp_b1ds        = 0x00000028,
-	.grp_b2ds        = 0x00000028,
-	.grp_b3ds        = 0x00000028,
-	.grp_b4ds        = 0x00000028,
-	.grp_b5ds        = 0x00000028,
-	.grp_b6ds        = 0x00000028,
-	.grp_b7ds        = 0x00000028,
-};
-
-static struct mx6_ddr_sysinfo ot1200_ddr_sysinfo = {
-	/* Width of data bus: 0=16, 1=32, 2=64 */
-	.dsize      = 2,
-	/* config for full 4GB range so that get_mem_size() works */
-	.cs_density = 32, /* 32Gb per CS */
-	/* Single chip select */
-	.ncs        = 1,
-	.cs1_mirror = 0,	/* war 0 */
-	.rtt_wr     = 1,	/* DDR3_RTT_60_OHM - RTT_Wr = RZQ/4 */
-	.rtt_nom    = 1,	/* DDR3_RTT_60_OHM - RTT_Nom = RZQ/4 */
-	.walat      = 1,	/* Write additional latency */
-	.ralat      = 5,	/* Read additional latency */
-	.mif3_mode  = 3,	/* Command prediction working mode */
-	.bi_on      = 1,	/* Bank interleaving enabled */	/* war 1 */
-	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
-	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
-	.refsel = 1,		/* Refresh cycles at 32KHz */
-	.refr = 7,		/* 8 refresh commands per refresh cycle */
-};
-
-/* MT41K128M16JT-125 */
-static struct mx6_ddr3_cfg micron_2gib_1600 = {
-	.mem_speed = 1600,
-	.density   = 2,
-	.width     = 16,
-	.banks     = 8,
-	.rowaddr   = 14,
-	.coladdr   = 10,
-	.pagesz    = 2,
-	.trcd      = 1375,
-	.trcmin    = 4875,
-	.trasmin   = 3500,
-	.SRT       = 1,
-};
-
-static struct mx6_mmdc_calibration micron_2gib_1600_mmdc_calib = {
-	/* write leveling calibration determine */
-	.p0_mpwldectrl0 = 0x00260025,
-	.p0_mpwldectrl1 = 0x00270021,
-	.p1_mpwldectrl0 = 0x00180034,
-	.p1_mpwldectrl1 = 0x00180024,
-	/* Read DQS Gating calibration */
-	.p0_mpdgctrl0   = 0x04380344,
-	.p0_mpdgctrl1   = 0x0330032C,
-	.p1_mpdgctrl0   = 0x0338033C,
-	.p1_mpdgctrl1   = 0x032C0300,
-	/* Read Calibration: DQS delay relative to DQ read access */
-	.p0_mprddlctl   = 0x3C2E3238,
-	.p1_mprddlctl   = 0x3A2E303C,
-	/* Write Calibration: DQ/DM delay relative to DQS write access */
-	.p0_mpwrdlctl   = 0x36384036,
-	.p1_mpwrdlctl   = 0x442E4438,
-};
-
-static void ot1200_spl_dram_init(void)
-{
-	mx6dq_dram_iocfg(64, &ot1200_ddr_ioregs, &ot1200_grp_ioregs);
-	mx6_dram_cfg(&ot1200_ddr_sysinfo, &micron_2gib_1600_mmdc_calib,
-		     &micron_2gib_1600);
-}
-
-/*
- * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
- * - we have a stack and a place to store GD, both in SRAM
- * - no variable global data is available
- */
-void board_init_f(ulong dummy)
-{
-	/* setup AIPS and disable watchdog */
-	arch_cpu_init();
-
-	/* iomux and setup of i2c */
-	board_early_init_f();
-
-	/* setup GP timer */
-	timer_init();
-
-	/* UART clocks enabled and gd valid - init serial console */
-	preloader_console_init();
-
-	/* configure MMDC for SDRAM width/size and per-model calibration */
-	ot1200_spl_dram_init();
-}
diff --git a/configs/ot1200_defconfig b/configs/ot1200_defconfig
deleted file mode 100644
index 45b9f2d41c..0000000000
--- a/configs/ot1200_defconfig
+++ /dev/null
@@ -1,55 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_TARGET_OT1200=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/bachmann/ot1200/mx6q_4x_mt41j128.cfg,MX6Q"
-CONFIG_BOOTDELAY=3
-CONFIG_USE_PREBOOT=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_MISC_INIT_R=y
-CONFIG_BOUNCE_BUFFER=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_DWC_AHSATA=y
-CONFIG_CMD_PCA953X=y
-CONFIG_FSL_USDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_BUS=2
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=25000000
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_SMSC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_DM_THERMAL=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/ot1200_spl_defconfig b/configs/ot1200_spl_defconfig
deleted file mode 100644
index 9472d29408..0000000000
--- a/configs/ot1200_spl_defconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
-CONFIG_TARGET_OT1200=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
-CONFIG_BOOTDELAY=3
-CONFIG_USE_PREBOOT=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_MISC_INIT_R=y
-CONFIG_BOUNCE_BUFFER=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_DWC_AHSATA=y
-CONFIG_CMD_PCA953X=y
-CONFIG_FSL_USDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_BUS=2
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=25000000
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_SMSC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_DM_THERMAL=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h
deleted file mode 100644
index 3a1ea0fc10..0000000000
--- a/include/configs/ot1200.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
- * Copyright (C) 2014 Bachmann electronic GmbH
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "mx6_common.h"
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
-
-/* UART Configs */
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE           UART1_BASE
-
-/* SF Configs */
-
-/* IO expander */
-#define CONFIG_PCA953X
-#define CONFIG_SYS_I2C_PCA953X_ADDR	0x20
-#define CONFIG_SYS_I2C_PCA953X_WIDTH	{ {0x20, 16} }
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED            100000
-
-/* OCOTP Configs */
-#define CONFIG_IMX_OTP
-#define IMX_OTP_BASE                    OCOTP_BASE_ADDR
-#define IMX_OTP_ADDR_MAX                0x7F
-#define IMX_OTP_DATA_ERROR_VAL          0xBADABADA
-#define IMX_OTPWRITE_ENABLED
-
-/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR      0
-#define CONFIG_SYS_FSL_USDHC_NUM       2
-
-/* USB Configs */
-#define CONFIG_MXC_USB_PORTSC   (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-
-/*
- * SATA Configs
- */
-#ifdef CONFIG_CMD_SATA
-#define CONFIG_SYS_SATA_MAX_DEVICE	1
-#define CONFIG_DWC_AHSATA_PORT_ID	0
-#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
-#define CONFIG_LBA48
-#endif
-
-/* SPL */
-#ifdef CONFIG_SPL
-#include "imx6_spl.h"
-#endif
-
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE                    ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE             MII100
-#define CONFIG_ETHPRIME                 "FEC"
-#define CONFIG_FEC_MXC_PHYADDR          0x5
-
-#ifndef CONFIG_SPL
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_I2C_EEPROM_BUS             1
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN        1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS     3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-#endif
-
-/* Thermal support */
-#define CONFIG_IMX_THERMAL
-
-/* Physical Memory Map */
-#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
-	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
-	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* Environment organization */
-/* M25P16 has an erase size of 64 KiB */
-
-#define CONFIG_BOOTP_SERVERIP
-#define CONFIG_BOOTP_BOOTFILE
-
-#endif         /* __CONFIG_H */
