From patchwork Tue Jun 30 10:33:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 243123 List-Id: U-Boot discussion From: sr at denx.de (Stefan Roese) Date: Tue, 30 Jun 2020 12:33:18 +0200 Subject: [PATCH v2 3/5] mips: octeon: octeon_ebb7304: Change TEXT_BASE to L2 cache In-Reply-To: <20200630103320.1290545-1-sr@denx.de> References: <20200630103320.1290545-1-sr@denx.de> Message-ID: <20200630103320.1290545-4-sr@denx.de> Change the linking address (TEXT_BASE) to point to the L2 cache. This way, mips_mach_early_init() will copy itself into L2 cache and run from there to improve the bootup speed. Also CONFIG_MIPS_CACHE_SETUP needs to be disabled, as now the cache is used at this time and can't be resetted. Signed-off-by: Stefan Roese --- (no changes since v1) configs/octeon_ebb7304_defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/configs/octeon_ebb7304_defconfig b/configs/octeon_ebb7304_defconfig index 0304b1ef8d..dc80fba848 100644 --- a/configs/octeon_ebb7304_defconfig +++ b/configs/octeon_ebb7304_defconfig @@ -1,5 +1,5 @@ CONFIG_MIPS=y -CONFIG_SYS_TEXT_BASE=0xffffffffbfc00000 +CONFIG_SYS_TEXT_BASE=0xffffffff80000000 CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x10000 @@ -7,6 +7,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_DEBUG_UART_BASE=0x8001180000000800 CONFIG_DEBUG_UART_CLOCK=1200000000 CONFIG_ARCH_OCTEON=y +# CONFIG_MIPS_CACHE_SETUP is not set CONFIG_DEBUG_UART=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_HUSH_PARSER=y