diff mbox series

[v1,2/4] clk: agilex: Add clock enable support

Message ID 20200710125523.68008-3-chee.hong.ang@intel.com
State New
Headers show
Series Agilex's clock driver updates and fixes | expand

Commit Message

Ang, Chee Hong July 10, 2020, 12:55 p.m. UTC 
From: Ley Foon Tan <ley.foon.tan at intel.com>

Some drivers probing failed if clock enable function is not supported in
clock driver. So, add clock enable function to clock driver to solve it.

Return 0 (success) for *.enable function because all clocks are enabled
by default in clock driver probe.

Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang at intel.com>
---
 drivers/clk/altera/clk-agilex.c | 6 ++++++
 1 file changed, 6 insertions(+)
diff mbox series

Patch

diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c
index 2ef9292f93..b5cf187364 100644
--- a/drivers/clk/altera/clk-agilex.c
+++ b/drivers/clk/altera/clk-agilex.c
@@ -542,6 +542,11 @@  static ulong socfpga_clk_get_rate(struct clk *clk)
 	}
 }
 
+static int socfpga_clk_enable(struct clk *clk)
+{
+	return 0;
+}
+
 static int socfpga_clk_probe(struct udevice *dev)
 {
 	const struct cm_config *cm_default_cfg = cm_get_default_config();
@@ -565,6 +570,7 @@  static int socfpga_clk_ofdata_to_platdata(struct udevice *dev)
 }
 
 static struct clk_ops socfpga_clk_ops = {
+	.enable		= socfpga_clk_enable,
 	.get_rate	= socfpga_clk_get_rate,
 };