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Wed, 21 Jul 2021 13:44:26 +0000 From: "Peng Fan (OSS)" To: sbabic@denx.de, festevam@gmail.com Cc: uboot-imx@nxp.com, u-boot@lists.denx.de, Peng Fan Subject: [PATCH V4 27/44] arm: imx8ulp: add rdc support Date: Wed, 21 Jul 2021 22:17:08 +0800 Message-Id: <20210721141725.23346-28-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210721141725.23346-1-peng.fan@oss.nxp.com> References: <20210721141725.23346-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SG2PR0401CA0015.apcprd04.prod.outlook.com (2603:1096:3:1::25) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by SG2PR0401CA0015.apcprd04.prod.outlook.com (2603:1096:3:1::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.21 via Frontend Transport; Wed, 21 Jul 2021 13:44:24 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9d3fd455-3702-475c-1a21-08d94c4da797 X-MS-TrafficTypeDiagnostic: DB6PR0402MB2757: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1332; 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Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 2 + arch/arm/mach-imx/imx8ulp/Makefile | 2 +- arch/arm/mach-imx/imx8ulp/rdc.c | 144 ++++++++++++++++++ 3 files changed, 147 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-imx/imx8ulp/rdc.c -- 2.30.0 diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h index a8f632f45e..47ee46bdf4 100644 --- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h +++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h @@ -13,4 +13,6 @@ extern unsigned long rom_pointer[]; ulong spl_romapi_raw_seekable_read(u32 offset, u32 size, void *buf); ulong spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev); enum bt_mode get_boot_mode(void); +int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm); +int xrdc_config_pdac_openacc(u32 bridge, u32 index); #endif diff --git a/arch/arm/mach-imx/imx8ulp/Makefile b/arch/arm/mach-imx/imx8ulp/Makefile index 78c81d78bb..1ef6cd5c91 100644 --- a/arch/arm/mach-imx/imx8ulp/Makefile +++ b/arch/arm/mach-imx/imx8ulp/Makefile @@ -4,4 +4,4 @@ # obj-y += lowlevel_init.o -obj-y += soc.o clock.o iomux.o pcc.o cgc.o +obj-y += soc.o clock.o iomux.o pcc.o cgc.o rdc.o diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c new file mode 100644 index 0000000000..7a098718da --- /dev/null +++ b/arch/arm/mach-imx/imx8ulp/rdc.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define XRDC_ADDR 0x292f0000 +#define MRC_OFFSET 0x2000 +#define MRC_STEP 0x200 + +#define SP(X) ((X) << 9) +#define SU(X) ((X) << 6) +#define NP(X) ((X) << 3) +#define NU(X) ((X) << 0) + +#define RWX 7 +#define RW 6 +#define R 4 +#define X 1 + +#define D7SEL_CODE (SP(RW) | SU(RW) | NP(RWX) | NU(RWX)) +#define D6SEL_CODE (SP(RW) | SU(RW) | NP(RWX)) +#define D5SEL_CODE (SP(RW) | SU(RWX)) +#define D4SEL_CODE SP(RWX) +#define D3SEL_CODE (SP(X) | SU(X) | NP(X) | NU(X)) +#define D0SEL_CODE 0 + +#define D7SEL_DAT (SP(RW) | SU(RW) | NP(RW) | NU(RW)) +#define D6SEL_DAT (SP(RW) | SU(RW) | NP(RW)) +#define D5SEL_DAT (SP(RW) | SU(RW) | NP(R) | NU(R)) +#define D4SEL_DAT (SP(RW) | SU(RW)) +#define D3SEL_DAT SP(RW) + +union dxsel_perm { + struct { + u8 dx; + u8 perm; + }; + + u32 dom_perm; +}; + +int xrdc_config_mrc_dx_perm(u32 mrc_con, u32 region, u32 dom, u32 dxsel) +{ + ulong w2_addr; + u32 val = 0; + + w2_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region * 0x20 + 0x8; + + val = (readl(w2_addr) & (~(7 << (3 * dom)))) | (dxsel << (3 * dom)); + writel(val, w2_addr); + + return 0; +} + +int xrdc_config_mrc_w0_w1(u32 mrc_con, u32 region, u32 w0, u32 size) +{ + ulong w0_addr, w1_addr; + + w0_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region * 0x20; + w1_addr = w0_addr + 4; + + if ((size % 32) != 0) + return -EINVAL; + + writel(w0 & ~0x1f, w0_addr); + writel(w0 + size - 1, w1_addr); + + return 0; +} + +int xrdc_config_mrc_w3_w4(u32 mrc_con, u32 region, u32 w3, u32 w4) +{ + ulong w3_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region * 0x20 + 0xC; + ulong w4_addr = w3_addr + 4; + + writel(w3, w3_addr); + writel(w4, w4_addr); + + return 0; +} + +int xrdc_config_pdac_openacc(u32 bridge, u32 index) +{ + ulong w0_addr; + u32 val; + + switch (bridge) { + case 3: + w0_addr = XRDC_ADDR + 0x1000 + 0x8 * index; + break; + case 4: + w0_addr = XRDC_ADDR + 0x1400 + 0x8 * index; + break; + case 5: + w0_addr = XRDC_ADDR + 0x1800 + 0x8 * index; + break; + default: + return -EINVAL; + } + writel(0xffffff, w0_addr); + + val = readl(w0_addr + 4); + writel(val | BIT(31), w0_addr + 4); + + return 0; +} + +int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm) +{ + ulong w0_addr; + u32 val; + + switch (bridge) { + case 3: + w0_addr = XRDC_ADDR + 0x1000 + 0x8 * index; + break; + case 4: + w0_addr = XRDC_ADDR + 0x1400 + 0x8 * index; + break; + case 5: + w0_addr = XRDC_ADDR + 0x1800 + 0x8 * index; + break; + default: + return -EINVAL; + } + val = readl(w0_addr); + writel((val & ~(0x7 << (dom * 3))) | (perm << (dom * 3)), w0_addr); + + val = readl(w0_addr + 4); + writel(val | BIT(31), w0_addr + 4); + + return 0; +}