From patchwork Sun Nov 7 21:33:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilias Apalodimas X-Patchwork-Id: 518017 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp2740059iml; Sun, 7 Nov 2021 13:33:55 -0800 (PST) X-Google-Smtp-Source: ABdhPJyLiuv7yjJSeIe2R5XjNX77I1F1rF/2h9fbEZG846WaJxRl0S2eyfQ+VhU/yHgR6iP0McyI X-Received: by 2002:a05:6402:6c8:: with SMTP id n8mr70289341edy.38.1636320835575; Sun, 07 Nov 2021 13:33:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1636320835; cv=none; d=google.com; s=arc-20160816; b=q/DgATd3k5bBqF1zzAsTDCLgAXWWVGIO8aCFuM/C5od2cFety3yOKqJNP4ia52lDjx pFWEZuZFD9zikb56Qb0oBvzv3OuuLNJVi/XdOdhzYWdcCGTcFK/tuN6BsiPLctrDhdQt s54B0lsM07haIky2F3DDrjPEN2vP+X11NSgCmRz+TYYVlkkDd4YQWvO4KTgS+R+cZK3H Ngonj7G8v2OFoPmn+Z7UNDOk7X1ONH02a8hY4csSEjYcV4sKIT+L2CjlnLnF7MWsGK4N Kjn3C0E8TN/l9OZjzS6eE2dGOwGB48d1/Zbrax+pgHLFJBeknfsxoLJXNbX+IS7bU1h3 og+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=UZyIk/VvX1j7zzkwXuvPHuxTWHVPnrmD0qjFM7LgOXs=; b=IiEUweOc2wykXVZuXgsYijerNFMQn+uDTpGxxUTDtDyn3rEb1fTVOF54QONeX2lzum 5aNFd0TxaOJmK2P1smi8yUrwRAK/mBNh9jPEGab6awJ+rzbwYiEGgxqZAQmv3lZD6HAW 9CgR1jjQZnGpZsPt7HbTffr4Dmsg7FtFzkm33Ea+MVcq6t7hhr6lh1M5Pm0AxnGA07Lo p7DZELNeH9/h5l00BVj95giMAz0MWUcK4zcVjp2t9yWS+4paSgfKL8QrgZsJ0mceT0e6 ynlVrWz2siCuJw/nDc7eqv7jkF/PEFnVyvmrYjYw9PLgZf+xBC505MPiNY4ShaHXzq0N fl4A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vAQOfigw; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id q19si27321228ejs.198.2021.11.07.13.33.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Nov 2021 13:33:55 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vAQOfigw; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8FD2083810; Sun, 7 Nov 2021 22:33:32 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="vAQOfigw"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 9E7FE837FC; Sun, 7 Nov 2021 22:33:28 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 0CC0B837EC for ; Sun, 7 Nov 2021 22:33:22 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ilias.apalodimas@linaro.org Received: by mail-ed1-x52b.google.com with SMTP id o8so54620805edc.3 for ; Sun, 07 Nov 2021 13:33:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UZyIk/VvX1j7zzkwXuvPHuxTWHVPnrmD0qjFM7LgOXs=; b=vAQOfigwAFUOE3rEj+dfb2wjnqaiq0VmjfwhiPx3u8Cn2t3D5I8tksOgBfsfC8JJLr SwM3LgpewVmuBKq/eS1k1EEwQBJuzUS5Y4e0Tc4sz14JDyIELCmngNM516dNk5qKHnzc NWVWiEa384t7N9f0rJcEYME8W4xIeaFM0ov+pSpgOPNFyTC2jtTij41jNq7hi13SFoRl vrKf0W4E0cOi0UlXRJys2pkif4FBM61aLGPRnLrfwy1MQqkKfS0QUJiH1SZyvjzQSh0w 8NcxfXbYfsr+bd4MUU7XxysgOA4KOdoyExNscSxf0+pmE/m8cTSfBpeAaOJ6RviIi3Q6 SRIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UZyIk/VvX1j7zzkwXuvPHuxTWHVPnrmD0qjFM7LgOXs=; b=jKMZSJ07lAvk6IHQBUtk6HBdgTCW5GI/EGfWlVIRbEuTaLGLIZXc6PGCdJwX0ugwLq F6LVfV/Vdrv0/2pyhgCUXK9JVvVXEePcuChIBKOV11nfWRqm/2LFZ80iytRc2LfiseCI WvxPmcwUPiF3vunwIbYOu06cPJCBsJDEEu4HY0Bals7mneyDK6m1+FrUUFR0v1YbX5OQ dAZTGhG4OwHMV07dwyRNRiwsATRqg5i6kVoOdar9QHqkxBWWE+hFc0uAXiuZrdfkrjDo 8iI15hWCCeilK2qXH80HZkkQnmZNUHrm+/Qsp4qRjqfpeZSi/HEqyc7Wly8CXG/l6sW6 IrCw== X-Gm-Message-State: AOAM532kKg+y309v9qZ15YNNoDJHMNKCe9TAGk/GVmiv2/taFYWQ3uPN 9lH06L0cUAd8tp7hA0p1S/WkP8zTuokdSw== X-Received: by 2002:aa7:d155:: with SMTP id r21mr91387872edo.341.1636320801621; Sun, 07 Nov 2021 13:33:21 -0800 (PST) Received: from apalos.home ([2a02:587:4680:8a9c:2e56:dcff:fe9a:8f06]) by smtp.gmail.com with ESMTPSA id hw8sm5042150ejc.58.2021.11.07.13.33.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Nov 2021 13:33:21 -0800 (PST) From: Ilias Apalodimas To: u-boot@lists.denx.de Cc: trini@konsulko.com, Ilias Apalodimas , Rick Chen , Sean Anderson , Simon Glass , Heinrich Schuchardt , Masahisa Kojima Subject: [PATCH 3/8 v6] tpm2: Introduce TIS tpm core Date: Sun, 7 Nov 2021 23:33:06 +0200 Message-Id: <20211107213312.263357-4-ilias.apalodimas@linaro.org> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211107213312.263357-1-ilias.apalodimas@linaro.org> References: <20211107213312.263357-1-ilias.apalodimas@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean There's a lot of code duplication in U-Boot right now. All the TPM TIS compatible drivers we have at the moment have their own copy of a TIS implementation. So let's create a common layer which implements the core TIS functions. Any driver added from now own, which is compatible with the TIS spec, will only have to provide the underlying bus communication mechanisms. Signed-off-by: Ilias Apalodimas --- drivers/tpm/tpm2_tis_core.c | 463 ++++++++++++++++++++++++++++++++++++ drivers/tpm/tpm_tis.h | 128 ++++++++++ include/tpm-v2.h | 1 + 3 files changed, 592 insertions(+) create mode 100644 drivers/tpm/tpm2_tis_core.c diff --git a/drivers/tpm/tpm2_tis_core.c b/drivers/tpm/tpm2_tis_core.c new file mode 100644 index 000000000000..ec8c730fe906 --- /dev/null +++ b/drivers/tpm/tpm2_tis_core.c @@ -0,0 +1,463 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020, Linaro Limited + * + * Based on the Linux TIS core interface and U-Boot original SPI TPM driver + */ + +#include +#include +#include +#include +#include +#include "tpm_tis.h" + +int tpm_tis_get_desc(struct udevice *dev, char *buf, int size) +{ + struct tpm_chip *chip = dev_get_priv(dev); + + if (size < 80) + return -ENOSPC; + + return snprintf(buf, size, + "%s v2.0: VendorID 0x%04x, DeviceID 0x%04x, RevisionID 0x%02x [%s]", + dev->name, chip->vend_dev & 0xFFFF, + chip->vend_dev >> 16, chip->rid, + (chip->is_open ? "open" : "closed")); +} + +/** + * tpm_tis_check_locality - Check the current TPM locality + * + * @dev: TPM device + * @loc: locality + * + * Return: True if the tested locality matches + */ +static bool tpm_tis_check_locality(struct udevice *dev, int loc) +{ + struct tpm_chip *chip = dev_get_priv(dev); + struct tpm_tis_phy_ops *phy_ops = chip->phy_ops; + u8 locality; + + phy_ops->read_bytes(dev, TPM_ACCESS(loc), 1, &locality); + if ((locality & (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID | + TPM_ACCESS_REQUEST_USE)) == + (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) { + chip->locality = loc; + return true; + } + + return false; +} + +/** + * tpm_tis_request_locality - Request a locality from the TPM + * + * @dev: TPM device + * @loc: requested locality + * + * Return: 0 on success -1 on failure + */ +int tpm_tis_request_locality(struct udevice *dev, int loc) +{ + struct tpm_chip *chip = dev_get_priv(dev); + struct tpm_tis_phy_ops *phy_ops = chip->phy_ops; + u8 buf = TPM_ACCESS_REQUEST_USE; + unsigned long start, stop; + + if (tpm_tis_check_locality(dev, loc)) + return 0; + + phy_ops->write_bytes(dev, TPM_ACCESS(loc), 1, &buf); + start = get_timer(0); + stop = chip->timeout_a; + do { + if (tpm_tis_check_locality(dev, loc)) + return 0; + mdelay(TPM_TIMEOUT_MS); + } while (get_timer(start) < stop); + + return -1; +} + +/** + * tpm_tis_status - Check the current device status + * + * @dev: TPM device + * @status: return value of status + * + * Return: 0 on success, negative on failure + */ +static int tpm_tis_status(struct udevice *dev, u8 *status) +{ + struct tpm_chip *chip = dev_get_priv(dev); + struct tpm_tis_phy_ops *phy_ops = chip->phy_ops; + + if (chip->locality < 0) + return -EINVAL; + + phy_ops->read_bytes(dev, TPM_STS(chip->locality), 1, status); + + if ((*status & TPM_STS_READ_ZERO)) { + log_err("TPM returned invalid status\n"); + return -EINVAL; + } + + return 0; +} + +/** + * tpm_tis_release_locality - Release the requested locality + * + * @dev: TPM device + * @loc: requested locality + * + * Return: 0 on success, negative on failure + */ +int tpm_tis_release_locality(struct udevice *dev, int loc) +{ + struct tpm_chip *chip = dev_get_priv(dev); + struct tpm_tis_phy_ops *phy_ops = chip->phy_ops; + u8 buf = TPM_ACCESS_ACTIVE_LOCALITY; + int ret; + + if (chip->locality < 0) + return 0; + + ret = phy_ops->write_bytes(dev, TPM_ACCESS(loc), 1, &buf); + chip->locality = -1; + + return ret; +} + +/** + * tpm_tis_wait_for_stat - Wait for TPM to become ready + * + * @dev: TPM device + * @mask: mask to match + * @timeout: timeout for retries + * @status: current status + * + * Return: 0 on success, negative on failure + */ +static int tpm_tis_wait_for_stat(struct udevice *dev, u8 mask, + unsigned long timeout, u8 *status) +{ + unsigned long start = get_timer(0); + unsigned long stop = timeout; + int ret; + + do { + mdelay(TPM_TIMEOUT_MS); + ret = tpm_tis_status(dev, status); + if (ret) + return ret; + + if ((*status & mask) == mask) + return 0; + } while (get_timer(start) < stop); + + return -ETIMEDOUT; +} + +/** + * tpm_tis_get_burstcount - Get the burstcount for the data FIFO + * + * @dev: TPM device + * @burstcount: current burstcount + * + * Return: 0 on success, negative on failure + */ +static int tpm_tis_get_burstcount(struct udevice *dev, size_t *burstcount) +{ + struct tpm_chip *chip = dev_get_priv(dev); + struct tpm_tis_phy_ops *phy_ops = chip->phy_ops; + unsigned long start, stop; + u32 burst; + + if (chip->locality < 0) + return -EINVAL; + + /* wait for burstcount */ + start = get_timer(0); + /* + * This is the TPMv2 defined timeout. Change this in case you want to + * make the driver compatile to TPMv1 + */ + stop = chip->timeout_a; + do { + phy_ops->read32(dev, TPM_STS(chip->locality), &burst); + *burstcount = (burst >> 8) & 0xFFFF; + if (*burstcount) + return 0; + + mdelay(TPM_TIMEOUT_MS); + } while (get_timer(start) < stop); + + return -ETIMEDOUT; +} + +/** + * tpm_tis_ready - Cancel pending comands and get the device on a ready state + * + * @dev: TPM device + * + * Return: 0 on success, negative on failure + */ +static int tpm_tis_ready(struct udevice *dev) +{ + struct tpm_chip *chip = dev_get_priv(dev); + struct tpm_tis_phy_ops *phy_ops = chip->phy_ops; + u8 data = TPM_STS_COMMAND_READY; + + /* This will cancel any pending commands */ + return phy_ops->write_bytes(dev, TPM_STS(chip->locality), 1, &data); +} + +int tpm_tis_send(struct udevice *dev, const u8 *buf, size_t len) +{ + struct tpm_chip *chip = dev_get_priv(dev); + struct tpm_tis_phy_ops *phy_ops = chip->phy_ops; + size_t burstcnt, wr_size, sent = 0; + u8 data = TPM_STS_GO; + u8 status; + int ret; + + if (!chip) + return -ENODEV; + + ret = tpm_tis_request_locality(dev, 0); + if (ret < 0) + return -EBUSY; + + ret = tpm_tis_status(dev, &status); + if (ret) + goto release_locality; + + if (!(status & TPM_STS_COMMAND_READY)) { + ret = tpm_tis_ready(dev); + if (ret) { + log_err("Can't cancel previous TPM operation\n"); + goto release_locality; + } + ret = tpm_tis_wait_for_stat(dev, TPM_STS_COMMAND_READY, + chip->timeout_b, &status); + if (ret) { + log_err("TPM not ready\n"); + goto release_locality; + } + } + + while (len > 0) { + ret = tpm_tis_get_burstcount(dev, &burstcnt); + if (ret) + goto release_locality; + + wr_size = min(len, burstcnt); + ret = phy_ops->write_bytes(dev, TPM_DATA_FIFO(chip->locality), + wr_size, buf + sent); + if (ret < 0) + goto release_locality; + + ret = tpm_tis_wait_for_stat(dev, TPM_STS_VALID, + chip->timeout_c, &status); + if (ret) + goto release_locality; + + sent += wr_size; + len -= wr_size; + /* make sure the TPM expects more data */ + if (len && !(status & TPM_STS_DATA_EXPECT)) { + ret = -EIO; + goto release_locality; + } + } + + /* + * Make a final check ensuring everything is ok and the TPM expects no + * more data + */ + ret = tpm_tis_wait_for_stat(dev, TPM_STS_VALID, chip->timeout_c, + &status); + if (ret) + goto release_locality; + + if (status & TPM_STS_DATA_EXPECT) { + ret = -EIO; + goto release_locality; + } + + ret = phy_ops->write_bytes(dev, TPM_STS(chip->locality), 1, &data); + if (ret) + goto release_locality; + + return sent; + +release_locality: + tpm_tis_ready(dev); + tpm_tis_release_locality(dev, chip->locality); + + return ret; +} + +static int tpm_tis_recv_data(struct udevice *dev, u8 *buf, size_t count) +{ + struct tpm_chip *chip = dev_get_priv(dev); + struct tpm_tis_phy_ops *phy_ops = chip->phy_ops; + int size = 0, len, ret; + size_t burstcnt; + u8 status; + + while (size < count && + tpm_tis_wait_for_stat(dev, TPM_STS_DATA_AVAIL | TPM_STS_VALID, + chip->timeout_c, &status) == 0) { + ret = tpm_tis_get_burstcount(dev, &burstcnt); + if (ret) + return ret; + + len = min_t(int, burstcnt, count - size); + ret = phy_ops->read_bytes(dev, TPM_DATA_FIFO(chip->locality), + len, buf + size); + if (ret < 0) + return ret; + + size += len; + } + + return size; +} + +/** + * tpm_tis_recv - Receive data from a device + * + * @dev: TPM device + * @buf: buffer to copy data + * @size: buffer size + * + * Return: bytes read or negative on failure + */ +int tpm_tis_recv(struct udevice *dev, u8 *buf, size_t count) +{ + struct tpm_chip *chip = dev_get_priv(dev); + int size, expected; + + if (count < TPM_HEADER_SIZE) + return -E2BIG; + + size = tpm_tis_recv_data(dev, buf, TPM_HEADER_SIZE); + if (size < TPM_HEADER_SIZE) { + log_err("TPM error, unable to read header\n"); + goto out; + } + + expected = get_unaligned_be32(buf + TPM_CMD_COUNT_OFFSET); + if (expected > count) { + size = -EIO; + log_warning("Too much data: %d > %zu\n", expected, count); + goto out; + } + + size += tpm_tis_recv_data(dev, &buf[TPM_HEADER_SIZE], + expected - TPM_HEADER_SIZE); + if (size < expected) { + log(LOGC_NONE, LOGL_ERR, + "TPM error, unable to read remaining bytes of result\n"); + size = -EIO; + goto out; + } + +out: + tpm_tis_ready(dev); + /* acquired in tpm_tis_send */ + tpm_tis_release_locality(dev, chip->locality); + + return size; +} + +int tpm_tis_cleanup(struct udevice *dev) +{ + struct tpm_chip *chip = dev_get_priv(dev); + + tpm_tis_ready(dev); + tpm_tis_release_locality(dev, chip->locality); + + return 0; +} + +int tpm_tis_open(struct udevice *dev) +{ + struct tpm_chip *chip = dev_get_priv(dev); + int ret; + + if (chip->is_open) + return -EBUSY; + + ret = tpm_tis_request_locality(dev, 0); + if (!ret) + chip->is_open = 1; + + return ret; +} + +void tpm_tis_ops_register(struct udevice *dev, struct tpm_tis_phy_ops *ops) +{ + struct tpm_chip *chip = dev_get_priv(dev); + + chip->phy_ops = ops; +} + +static bool tis_check_ops(struct tpm_tis_phy_ops *phy_ops) +{ + if (!phy_ops || !phy_ops->read_bytes || !phy_ops->write_bytes || + !phy_ops->read32 || !phy_ops->write32) + return false; + + return true; +} + +int tpm_tis_init(struct udevice *dev) +{ + struct tpm_chip *chip = dev_get_priv(dev); + struct tpm_tis_phy_ops *phy_ops = chip->phy_ops; + int ret; + u32 tmp; + + if (!tis_check_ops(phy_ops)) { + log_err("Driver bug. No bus ops defined\n"); + return -1; + } + ret = tpm_tis_request_locality(dev, 0); + if (ret) + return ret; + + chip->timeout_a = TIS_SHORT_TIMEOUT_MS; + chip->timeout_b = TIS_LONG_TIMEOUT_MS; + chip->timeout_c = TIS_SHORT_TIMEOUT_MS; + chip->timeout_d = TIS_SHORT_TIMEOUT_MS; + + /* Disable interrupts */ + phy_ops->read32(dev, TPM_INT_ENABLE(chip->locality), &tmp); + tmp |= TPM_INTF_CMD_READY_INT | TPM_INTF_LOCALITY_CHANGE_INT | + TPM_INTF_DATA_AVAIL_INT | TPM_INTF_STS_VALID_INT; + tmp &= ~TPM_GLOBAL_INT_ENABLE; + phy_ops->write32(dev, TPM_INT_ENABLE(chip->locality), tmp); + + phy_ops->read_bytes(dev, TPM_RID(chip->locality), 1, &chip->rid); + phy_ops->read32(dev, TPM_DID_VID(chip->locality), &chip->vend_dev); + + return tpm_tis_release_locality(dev, chip->locality); +} + +int tpm_tis_close(struct udevice *dev) +{ + struct tpm_chip *chip = dev_get_priv(dev); + int ret = 0; + + if (chip->is_open) { + ret = tpm_tis_release_locality(dev, chip->locality); + chip->is_open = 0; + } + + return ret; +} diff --git a/drivers/tpm/tpm_tis.h b/drivers/tpm/tpm_tis.h index 2a160fe05c9a..7a69bace6828 100644 --- a/drivers/tpm/tpm_tis.h +++ b/drivers/tpm/tpm_tis.h @@ -21,6 +21,65 @@ #include #include +/** + * struct tpm_tis_phy_ops - low-level TPM bus operations + */ +struct tpm_tis_phy_ops { + /* read_bytes() - Read a number of bytes from the device + * + * @udev: TPM device + * @addr: offset from device base + * @len: len to read + * @result: data read + */ + int (*read_bytes)(struct udevice *udev, u32 addr, u16 len, + u8 *result); + /* write_bytes() - Read a number of bytes from the device + * + * @udev: TPM device + * @addr: offset from device base + * @len: len to read + * @value: data to write + */ + int (*write_bytes)(struct udevice *udev, u32 addr, u16 len, + const u8 *value); + /* read32() - Read a 32bit value of the device + * + * @udev: TPM device + * @addr: offset from device base + * @result: data read + */ + int (*read32)(struct udevice *udev, u32 addr, u32 *result); + /* write32() - write a 32bit value to the device + * + * @udev: TPM device + * @addr: offset from device base + * @src: data to write + */ + int (*write32)(struct udevice *udev, u32 addr, u32 src); +}; + +enum tis_int_flags { + TPM_GLOBAL_INT_ENABLE = 0x80000000, + TPM_INTF_BURST_COUNT_STATIC = 0x100, + TPM_INTF_CMD_READY_INT = 0x080, + TPM_INTF_INT_EDGE_FALLING = 0x040, + TPM_INTF_INT_EDGE_RISING = 0x020, + TPM_INTF_INT_LEVEL_LOW = 0x010, + TPM_INTF_INT_LEVEL_HIGH = 0x008, + TPM_INTF_LOCALITY_CHANGE_INT = 0x004, + TPM_INTF_STS_VALID_INT = 0x002, + TPM_INTF_DATA_AVAIL_INT = 0x001, +}; + +#define TPM_ACCESS(l) (0x0000 | ((l) << 12)) +#define TPM_INT_ENABLE(l) (0x0008 | ((l) << 12)) +#define TPM_STS(l) (0x0018 | ((l) << 12)) +#define TPM_DATA_FIFO(l) (0x0024 | ((l) << 12)) +#define TPM_DID_VID(l) (0x0f00 | ((l) << 12)) +#define TPM_RID(l) (0x0f04 | ((l) << 12)) +#define TPM_INTF_CAPS(l) (0x0014 | ((l) << 12)) + enum tpm_timeout { TPM_TIMEOUT_MS = 5, TIS_SHORT_TIMEOUT_MS = 750, @@ -43,6 +102,7 @@ struct tpm_chip { u8 rid; unsigned long timeout_a, timeout_b, timeout_c, timeout_d; /* msec */ ulong chip_type; + struct tpm_tis_phy_ops *phy_ops; }; struct tpm_input_header { @@ -130,4 +190,72 @@ enum tis_status { }; #endif +/** + * tpm_tis_open - Open the device and request locality 0 + * + * @dev: TPM device + * + * Return: 0 on success, negative on failure + */ +int tpm_tis_open(struct udevice *udev); +/** + * tpm_tis_close - Close the device and release locality + * + * @dev: TPM device + * + * Return: 0 on success, negative on failure + */ +int tpm_tis_close(struct udevice *udev); +/** tpm_tis_cleanup - Get the device in ready state and release locality + * + * @dev: TPM device + * + * Return: always 0 + */ +int tpm_tis_cleanup(struct udevice *udev); +/** + * tpm_tis_send - send data to the device + * + * @dev: TPM device + * @buf: buffer to send + * @len: size of the buffer + * + * Return: number of bytes sent or negative on failure + */ +int tpm_tis_send(struct udevice *udev, const u8 *buf, size_t len); +/** + * tpm_tis_recv_data - Receive data from a device. Wrapper for tpm_tis_recv + * + * @dev: TPM device + * @buf: buffer to copy data + * @size: buffer size + * + * Return: bytes read or negative on failure + */ +int tpm_tis_recv(struct udevice *udev, u8 *buf, size_t count); +/** + * tpm_tis_get_desc - Get the TPM description + * + * @dev: TPM device + * @buf: buffer to fill data + * @size: buffer size + * + * @Return: Number of characters written (or would have been written) in buffer + */ +int tpm_tis_get_desc(struct udevice *udev, char *buf, int size); +/** + * tpm_tis_init - inititalize the device + * + * @dev: TPM device + * + * Return: 0 on success, negative on failure + */ +int tpm_tis_init(struct udevice *udev); +/** + * tpm_tis_ops_register - register the PHY ops for the device + * + * @dev: TPM device + * @ops: tpm_tis_phy_ops ops for the device + */ +void tpm_tis_ops_register(struct udevice *udev, struct tpm_tis_phy_ops *ops); #endif diff --git a/include/tpm-v2.h b/include/tpm-v2.h index 13b3db67c60f..e6b68769f3ff 100644 --- a/include/tpm-v2.h +++ b/include/tpm-v2.h @@ -396,6 +396,7 @@ enum { TPM_STS_DATA_EXPECT = 1 << 3, TPM_STS_SELF_TEST_DONE = 1 << 2, TPM_STS_RESPONSE_RETRY = 1 << 1, + TPM_STS_READ_ZERO = 0x23 }; enum {