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[206.248.184.2]) by smtp.gmail.com with ESMTPSA id mi4-20020a056214558400b005ef6557834fsm3183223qvb.62.2023.05.12.13.15.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 13:15:31 -0700 (PDT) From: Ralph Siemsen To: u-boot@lists.denx.de Cc: Marek Vasut , Ralph Siemsen , Marek Vasut Subject: [PATCH v5 01/10] ARM: armv7: add non-SPL enable for Cortex SMPEN Date: Fri, 12 May 2023 16:15:13 -0400 Message-Id: <20230512201522.2295937-2-ralph.siemsen@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230512201522.2295937-1-ralph.siemsen@linaro.org> References: <20230512201522.2295937-1-ralph.siemsen@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S") added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For platforms not using SPL boot, add the corresponding non-SPL config, so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected. Signed-off-by: Ralph Siemsen Reviewed-by: Marek Vasut --- This will be used by the following commit that adds RZ/N1 support. (no changes since v5) Changes in v5: - add R-b tag arch/arm/cpu/armv7/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig index f1e4e26b8f..e33e53636a 100644 --- a/arch/arm/cpu/armv7/Kconfig +++ b/arch/arm/cpu/armv7/Kconfig @@ -107,6 +107,11 @@ config ARMV7_LPAE Say Y here to use the long descriptor page table format. This is required if U-Boot runs in HYP mode. +config ARMV7_SET_CORTEX_SMPEN + bool + help + Enable the ARM Cortex ACTLR.SMP enable bit in U-boot. + config SPL_ARMV7_SET_CORTEX_SMPEN bool help