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a=openpgp-sha256; l=3691; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=dkjlxIYjmZqHcciS/NcT6tSSQUIBu5Zi+tWMsHILD6o=; b=owEBbQKS/ZANAwAIAQWDMSsZX2S2AcsmYgBmE+w01CVhWGC7dUsuA7Oyeyzg/uNYauPpfcIzI VTmQ6CLGVGJAjMEAAEIAB0WIQS2UaFGPGq+0GkMVc0FgzErGV9ktgUCZhPsNAAKCRAFgzErGV9k tk3OD/wJ/7ryHgEywbVDumIwh0WCzdyukrv5jXpLKmu7v3Ci/lejGSDvjZUB6KY7N2k6jeNq2+M 5XqX99yAbuSG8ZOLv32oY7CMKkSKis1nvxEQM5aW0iSEVAZqgummH7+x1yR0LbxdUz17+heRE05 AP7ys/6VkHdbkgXFQJbSIzY5xzVDWCgwqsNnrbqqkGLAHfUWs9rNZMtwBvrXu+uyqrDerYXTxNb 29LGFB+zeswxXpqGWBSrWkmjpJZL3CfjoUCTmwRLGOVMHRu2zPKhmc+MA1GSQRFu6wwHzvGBR4e ogu8yenVvvXwept6Ty9wVDVQI5nji6Ji7Etw3KwxWddKU9UZKU8EHtJXNiqPh6Y2Z/cRLjFb7H4 MLgSnzsgJkD81L2WQHSnwPjMHzDYXKVkF/QguM6nTsYMXqdWgZtkug7jYEKSpR8e0QrxPjjk8XM nF2MNBsXCSImGxp3x1iQflSqVg5VAyK9dD8ef5EN0DSVWv++mD0ZCIRDPQqkFkdXekN8pcZYzeC hufb2Ft+lPdgnIGJBj9t3IIVABxEgVAPz5qZUSUX6RKu75CB+DivHjRFeW1U+cN87yvlw7GNkgU nJQ9ANXLh0nmn+MlwXlTjb0ggulJ7MuwkBylGlZKS6MqYefS48p70t8qZFX49w9GeNrI3RMsFTR UdYtrR95BPWghBg== X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean This SoC has a basic pinctrl block with no tiles. Signed-off-by: Caleb Connolly --- drivers/pinctrl/qcom/Kconfig | 7 ++++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-qcm2290.c | 67 ++++++++++++++++++++++++++++++++++ 3 files changed, 75 insertions(+) diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 2fe639814785..35140efd5b62 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -26,8 +26,15 @@ config PINCTRL_QCOM_IPQ4019 help Say Y here to enable support for pinctrl on the IPQ4019 SoC, as well as the associated GPIO driver. +config PINCTRL_QCOM_QCM2290 + bool "Qualcomm QCM2290 GCC" + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the Snapdragon QCM2290 SoC, + as well as the associated GPIO driver. + config PINCTRL_QCOM_QCS404 bool "Qualcomm QCS404 GCC" select PINCTRL_QCOM help diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 6d9aca6d7b7e..0b1d610ea3e8 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_PINCTRL_QCOM) += pinctrl-qcom.o obj-$(CONFIG_PINCTRL_QCOM_APQ8016) += pinctrl-apq8016.o obj-$(CONFIG_PINCTRL_QCOM_IPQ4019) += pinctrl-ipq4019.o obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o +obj-$(CONFIG_PINCTRL_QCOM_QCM2290) += pinctrl-qcm2290.o obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o diff --git a/drivers/pinctrl/qcom/pinctrl-qcm2290.c b/drivers/pinctrl/qcom/pinctrl-qcm2290.c new file mode 100644 index 000000000000..e2abb53ba4e5 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-qcm2290.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm qcm2290 pinctrl + * + * (C) Copyright 2024 Linaro Ltd. + * + */ + +#include + +#include "pinctrl-qcom.h" + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); + +static const struct pinctrl_function msm_pinctrl_functions[] = { + { "qup4", 1 }, + { "gpio", 0 }, +}; + +static const char *qcm2290_get_function_name(struct udevice *dev, unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *qcm2290_get_pin_name(struct udevice *dev, unsigned int selector) +{ + static const char *const special_pins_names[] = { + "sdc1_rclk", "sdc1_clk", "sdc1_cmd", "sdc1_data", + "sdc2_clk", "sdc2_cmd", "sdc2_data", + }; + + if (selector >= 127 && selector <= 133) + snprintf(pin_name, MAX_PIN_NAME_LEN, special_pins_names[selector - 127]); + else + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + + return pin_name; +} + +static unsigned int qcm2290_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +struct msm_pinctrl_data qcm2290_data = { + .pin_data = { + .pin_count = 133, + .special_pins_start = 127, + }, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = qcm2290_get_function_name, + .get_function_mux = qcm2290_get_function_mux, + .get_pin_name = qcm2290_get_pin_name, +}; + +static const struct udevice_id msm_pinctrl_ids[] = { { .compatible = "qcom,qcm2290-tlmm", + .data = (ulong)&qcm2290_data }, + { /* Sentinal */ } }; + +U_BOOT_DRIVER(pinctrl_qcm2290) = { + .name = "pinctrl_qcm2290", + .id = UCLASS_NOP, + .of_match = msm_pinctrl_ids, + .ops = &msm_pinctrl_ops, + .bind = msm_pinctrl_bind, +};