From patchwork Fri Apr 12 09:54:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 788280 Delivered-To: patch@linaro.org Received: by 2002:adf:e6ca:0:b0:346:15ad:a2a with SMTP id y10csp631192wrm; Fri, 12 Apr 2024 02:55:17 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXfTEeetShWEzKObCbw5T3Tlg7/hUIM9YIeM4UhcSyi2OU/CgR/6/uuvDN4zg0Q2zCKhV4OJXqN5ERuz67GoNEP X-Google-Smtp-Source: AGHT+IEM/8PBn/uy6hrMGmaDeSeoxvevo7LGJywgALxP7LoDEsTSXuRlhM8+2QM1VK1LynTInTHh X-Received: by 2002:a50:8754:0:b0:56e:2a38:1fb3 with SMTP id 20-20020a508754000000b0056e2a381fb3mr1870937edv.4.1712915717563; Fri, 12 Apr 2024 02:55:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1712915717; cv=none; d=google.com; s=arc-20160816; b=PiR1o7zhBfbQhVCnsf4gYBjpokbz8zpNtEi9G061LC9N2WWIeFxZF+VkVLWRzu+qXL BhGvitQDMPT+8Q5x6oIokGk7kQd0qIvLnTienaJqxtUZ++iFBVJyAEpMjE4BijOan7D8 1eAGM79rLguZ38baDubDP2JYp8bUgqw4WIzZ6ZBQA7Pb565rNmBSkPr7b7Pe7WuGRQZG kAYPT7PRtoMxKelnc/7lfXdJxnHjDMzM+zfGan4KSlJ/U4wgRC7nAfbQW4G6/RfHGc9y PXXyTFuul/OwHMWZoRTC7vMvNZeMo36y73pN9buAHqTt4MXmgc8HD7mA/iDp97RaQ/L0 yzsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=3AUYOq/ItyiLEj7tgmFcxT0Ld2W+iat/2830EavHflU=; fh=T5H15yVH0x76eljP78R1SA5aX1AOqAQ+w8cgext4uuk=; b=kXUFceU8l0sprWqFPuWrqysN/0Q0qNWWL5NLzr+xK6GGplntrbS2289FqKE3XBm0CR vja68xzZRdHn1jfGMhyZDDKpq5FzCuNaE/NXkNgvRV4Fhyg4A522ExXr91Iq7Oorz/5R AJ61Vtqh0SnHiP2QtlWNHIapBuUDdsPkKiGX+CbGjzwpPQ/v8G3uHCvi3GAZscFt03cK baOTG58+k0M+Ax12Dh60NeTY4QZhp0yiYa/vttJfTI6kDTMvrLkHSVt1A9xVsAyCB2NQ HTnCXlERP0Dz2qYFKsmddKaFQRfE+3uOvg8b85GwlSXZYN2KMBN6maIOfnBXWOgDRB68 zH2g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IafP0z1M; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id g19-20020a50d5d3000000b00568386368c5si1489635edj.690.2024.04.12.02.55.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Apr 2024 02:55:17 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IafP0z1M; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C0814880A8; Fri, 12 Apr 2024 11:55:04 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="IafP0z1M"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 7158587E01; Fri, 12 Apr 2024 11:55:03 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: * X-Spam-Status: No, score=1.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_SBL_CSS,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.2 Received: from mail-oa1-x32.google.com (mail-oa1-x32.google.com [IPv6:2001:4860:4864:20::32]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id DBAFE881A8 for ; Fri, 12 Apr 2024 11:54:59 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sumit.garg@linaro.org Received: by mail-oa1-x32.google.com with SMTP id 586e51a60fabf-23333dddd8aso490478fac.1 for ; Fri, 12 Apr 2024 02:54:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1712915698; x=1713520498; darn=lists.denx.de; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3AUYOq/ItyiLEj7tgmFcxT0Ld2W+iat/2830EavHflU=; b=IafP0z1Me3DHMn69NYv8O7rQ4SpnvzGA+zU1jF8oTDIEjjfuGLlVgKCaA3Kx2Iig5J 1YEjFN4cO5EOk7njXKh3LLn68HZj8UFnYSxKFB/db4H+UP/Q7A4OfBmIxoBJ7uoOoWlJ QRGjsw1k34FKtnrsQOxst6/RdT++YoSlV51UJu7oXkYqKAfTIJg1VW2zqDMN9CRW9K/a kBe6LQbt8RFpWL0vy0tkotQobjDCzy/RUEr/eb3NMnW7Kze1OgFN5vvGv1ZBBU7qEm1e um54fM9ptsv2283FkMdiKZWuJJ6+QrkDgPxpxILy8RTjuEZjZVLk5l0Bi/M9DegTp9wq p3zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712915698; x=1713520498; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3AUYOq/ItyiLEj7tgmFcxT0Ld2W+iat/2830EavHflU=; b=hnLdQg2vmUk1dwQxcA8s/wHYrZhYmexs5ZU4LLkcizKgWJTHx4GINWm7ZBQqYWEwQK oZOheUnF50CfVNgmHf7s5eLsAEO+S5GHc7WQ2X71xAVmm2BlqxsOeYELhNVwjKYwVjhk 4gnOyZJF3aucdfx9dsdBuvj+NCzbrm0d9l6RoFGuFVv8cRrwyWHOhKU6xDPNhoYXEVul LgxAU3Q6m9GRTJpBruKU3CUN50JS/qdwNX0ClgfWn0tEfbxjFoELZi0ljL/J7FYLlivW g7fSA1yhiWKjjyL5iExagF9A5tUbRHdlv7pkJX1uThao26q/WtB9M5EEimYTevyYSJoI UvnQ== X-Gm-Message-State: AOJu0YyBLZaDXKFW2XpN23vV5o9vNyOGln7vuVtV+Wl7fLMMxhyN+cgf 9muRg/mLHTay8yoQHANEYJHkiNk+UDV93e0Tq6NDlFtFOGS+WJ+W1gYtQNRUUM7evWHkUPn7eMV y X-Received: by 2002:a05:6870:1656:b0:22e:8406:5bc4 with SMTP id c22-20020a056870165600b0022e84065bc4mr2209238oae.32.1712915698355; Fri, 12 Apr 2024 02:54:58 -0700 (PDT) Received: from sumit-X1.. ([223.178.210.92]) by smtp.gmail.com with ESMTPSA id bn19-20020a056a00325300b006ed0b798f1fsm2534839pfb.119.2024.04.12.02.54.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Apr 2024 02:54:58 -0700 (PDT) From: Sumit Garg To: u-boot@lists.denx.de Cc: caleb.connolly@linaro.org, neil.armstrong@linaro.org, trini@konsulko.com, lukma@denx.de, seanga2@gmail.com, sjg@chromium.org, laetitia.mariottini@se.com, pascal.eberhard@se.com, abdou.saker@se.com, jimmy.lalande@se.com, benjamin.missey@non.se.com, daniel.thompson@linaro.org, stephan@gerhold.net, Sumit Garg Subject: [PATCH v4 2/7] apq8016: Add support for UART1 clocks and pinmux Date: Fri, 12 Apr 2024 15:24:33 +0530 Message-Id: <20240412095438.410570-3-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240412095438.410570-1-sumit.garg@linaro.org> References: <20240412095438.410570-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean SE HMIBSC board uses UART1 as the main debug console, so add corresponding clocks and pinmux support. Along with that update instructions to enable clocks for debug UART support. Reviewed-by: Caleb Connolly Signed-off-by: Sumit Garg --- drivers/clk/qcom/clock-apq8016.c | 38 ++++++++++++++++++-------- drivers/pinctrl/qcom/pinctrl-apq8016.c | 1 + drivers/serial/serial_msm.c | 11 ++++++-- 3 files changed, 35 insertions(+), 15 deletions(-) diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index 5a5868169c8..9556b94774a 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -31,7 +31,8 @@ #define BLSP1_AHB_CBCR 0x1008 /* Uart clock control registers */ -#define BLSP1_UART2_BCR (0x3028) +#define BLSP1_UART1_APPS_CBCR (0x203C) +#define BLSP1_UART1_APPS_CMD_RCGR (0x2044) #define BLSP1_UART2_APPS_CBCR (0x302C) #define BLSP1_UART2_APPS_CMD_RCGR (0x3034) @@ -52,7 +53,7 @@ static struct vote_clk gcc_blsp1_ahb_clk = { }; /* SDHCI */ -static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) +static int apq8016_clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) { int div = 15; /* 100MHz default */ @@ -70,20 +71,35 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) } /* UART: 115200 */ -int apq8016_clk_init_uart(phys_addr_t base) +int apq8016_clk_init_uart(phys_addr_t base, unsigned long id) { + u32 cmd_rcgr, apps_cbcr; + + switch (id) { + case GCC_BLSP1_UART1_APPS_CLK: + cmd_rcgr = BLSP1_UART1_APPS_CMD_RCGR; + apps_cbcr = BLSP1_UART1_APPS_CBCR; + break; + case GCC_BLSP1_UART2_APPS_CLK: + cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR; + apps_cbcr = BLSP1_UART2_APPS_CBCR; + break; + default: + return 0; + } + /* Enable AHB clock */ clk_enable_vote_clk(base, &gcc_blsp1_ahb_clk); /* 7372800 uart block clock @ GPLL0 */ - clk_rcg_set_rate_mnd(base, BLSP1_UART2_APPS_CMD_RCGR, 1, 144, 15625, - CFG_CLK_SRC_GPLL0, 16); + clk_rcg_set_rate_mnd(base, cmd_rcgr, 1, 144, 15625, CFG_CLK_SRC_GPLL0, + 16); /* Vote for gpll0 clock */ clk_enable_gpll0(base, &gpll0_vote_clk); /* Enable core clk */ - clk_enable_cbc(base + BLSP1_UART2_APPS_CBCR); + clk_enable_cbc(base + apps_cbcr); return 0; } @@ -94,14 +110,12 @@ static ulong apq8016_clk_set_rate(struct clk *clk, ulong rate) switch (clk->id) { case GCC_SDCC1_APPS_CLK: /* SDC1 */ - return clk_init_sdc(priv, 0, rate); - break; + return apq8016_clk_init_sdc(priv, 0, rate); case GCC_SDCC2_APPS_CLK: /* SDC2 */ - return clk_init_sdc(priv, 1, rate); - break; + return apq8016_clk_init_sdc(priv, 1, rate); + case GCC_BLSP1_UART1_APPS_CLK: /* UART1 */ case GCC_BLSP1_UART2_APPS_CLK: /* UART2 */ - return apq8016_clk_init_uart(priv->base); - break; + return apq8016_clk_init_uart(priv->base, clk->id); default: return 0; } diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c index a9a00f4b081..1ee8b7db1a2 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8016.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c @@ -29,6 +29,7 @@ static const char * const msm_pinctrl_pins[] = { }; static const struct pinctrl_function msm_pinctrl_functions[] = { + {"blsp_uart1", 2}, {"blsp_uart2", 2}, }; diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c index ac4280c6c4c..4de10e75191 100644 --- a/drivers/serial/serial_msm.c +++ b/drivers/serial/serial_msm.c @@ -248,12 +248,17 @@ static struct msm_serial_data init_serial_data = { #include /* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916 */ -//int apq8016_clk_init_uart(phys_addr_t gcc_base); +//int apq8016_clk_init_uart(phys_addr_t gcc_base, unsigned long id); static inline void _debug_uart_init(void) { - /* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916 */ - //apq8016_clk_init_uart(0x1800000); + /* + * Uncomment to turn on UART clocks when debugging U-Boot as aboot + * on MSM8916. Supported debug UART clock IDs: + * - db410c: GCC_BLSP1_UART2_APPS_CLK + * - HMIBSC: GCC_BLSP1_UART1_APPS_CLK + */ + //apq8016_clk_init_uart(0x1800000, ); uart_dm_init(&init_serial_data); }