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[92.17.96.232]) by smtp.gmail.com with ESMTPSA id p7-20020a05600c358700b004182cd07133sm9040333wmq.3.2024.04.15.08.03.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Apr 2024 08:03:42 -0700 (PDT) From: Caleb Connolly Date: Mon, 15 Apr 2024 16:03:39 +0100 Subject: [PATCH v2 2/3] clk/qcom: ipq4019: return valid rate when setting UART clock MIME-Version: 1.0 Message-Id: <20240415-b4-msm-serial-bitrate-v2-2-b7a048adc6a3@linaro.org> References: <20240415-b4-msm-serial-bitrate-v2-0-b7a048adc6a3@linaro.org> In-Reply-To: <20240415-b4-msm-serial-bitrate-v2-0-b7a048adc6a3@linaro.org> To: Lukasz Majewski , Sean Anderson , Caleb Connolly , Neil Armstrong , Sumit Garg , Tom Rini Cc: Robert Marko , u-boot-qcom@groups.io, u-boot@lists.denx.de X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=979; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=jbE4uxM05hys6K6aPZcowyfpb9rgLC2loD8Pu1qX1Mc=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhjRZx9M3F256+5Wh45rBuoxbjiniNZxzj3/es3zz5f0MQ WUNTjIhHaUsDIIcDLJiiiziJ5ZZNq29bK+xfcEFmDmsTCBDGLg4BWAit/4wMsz4O8/v3Ncg0aeJ Emtc+makL1De+ujl54iDmT8Z2j8U2HAy/OFo+R3v1/li2gMGy+319r5d8XNLzjRaBBxPEw1s5T6 kNBkA X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean clk_set_rate() should return the clock rate that was set. The IPQ4019 clock driver doesn't set any rates yet but it should still return the expected value so that drivers can work properly. For a baud rate of 115200 with an expected bit clock divisor of 16, the clock rate should be 1843200 so return that frequency. Signed-off-by: Caleb Connolly --- drivers/clk/qcom/clock-ipq4019.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clock-ipq4019.c b/drivers/clk/qcom/clock-ipq4019.c index d693776d339d..72f235eab212 100644 --- a/drivers/clk/qcom/clock-ipq4019.c +++ b/drivers/clk/qcom/clock-ipq4019.c @@ -20,9 +20,9 @@ static ulong ipq4019_clk_set_rate(struct clk *clk, ulong rate) { switch (clk->id) { case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/ /* This clock is already initialized by SBL1 */ - return 0; + return 1843200; default: return -EINVAL; } }