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Fri, 19 Jul 2024 06:56:55 -0700 (PDT) From: Neil Armstrong Date: Fri, 19 Jul 2024 15:56:51 +0200 Subject: [PATCH 2/3] usb: dwc3: fix dcache flush range calculation MIME-Version: 1.0 Message-Id: <20240719-u-boot-dwc3-gadget-dcache-fixup-v1-2-58a5f026ea8e@linaro.org> References: <20240719-u-boot-dwc3-gadget-dcache-fixup-v1-0-58a5f026ea8e@linaro.org> In-Reply-To: <20240719-u-boot-dwc3-gadget-dcache-fixup-v1-0-58a5f026ea8e@linaro.org> To: Marek Vasut , Tom Rini , Lukasz Majewski , Mattijs Korpershoek Cc: Caleb Connolly , u-boot-qcom@groups.io, u-boot@lists.denx.de, Neil Armstrong X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1110; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=kh4rtOL6KeUvZru5sLtHZtD07pAad6NFUjKXTJm+qDc=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBmmnClPPG/Fg9c6HqnGAbU3NOHqXuMzkT+XVYeFAfF bSfTPJGJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZppwpQAKCRB33NvayMhJ0Y3sEA CVFcj2sDoJHJIuKiiCDOwm2HfJ/xEIjAqoiZ9UFFgegJjWBWvWHgvkLP2t9hf3oRIMeV9Ifq0CkXyx iAsGxXjqjSuyvzKC0s7JORHI11qqWvICHEIfvuqfVnkNsyX8dZZ42VZA/u01sKF1hR+dY9UWQylvgC FzyDUI1q7ZtyhL0qVHnRFsjHgS4BPaHsYXoDYku+rrbSEewXB0X/oDlYX5JBDSDwEk2aM/nSOjm8vz EgSCREGm/uX3OfdY8MpbqbSFF8rkLAsqsrzGxMVYA1izmevlztjxwbIFjFktyZ6secS+pDAbHKsKvl sKiaAJc9EGpowHdfS+YBBxcRpmQ//MoHts5zaxmM+oiJY1ds4s4UpGBQH6YoyfvgPka7H9xOGr0vvt n/YPk9jL1KKgcruDyyfshQTylnuDGUXpDYbxui6CQ3sRDedNFWMWir1PMBlWE9712SVc2YWkbQLIE2 lR56Ivp/A+z+k4Msrypy7ObTaKR4KZ+gMRE8LwNdZbSak8qhxFW8ciKrPwZ+BCz/oGECXpaT7M8zs8 VntXCS/LfYuWsl9R3wULTraYYcAPjb3eAmulIiju/8l/47y9hy01pPsxBVUktyAhS/cGtLtnoaLKKB 9zj9MFLlAVLHhgPpTbmJKOWcbORorS1k/4RIMXQsuFCFc2PQJFU/Q9nlcXUQ== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The current flush operation will omit doing a flush/invalidate on the first and last bytes if the base address and size are not aligned with DMA_MINALIGN. This causes operation failures Qualcomm platforms. Take in account the alignment and size of the buffer and also flush the previous and last cacheline. Signed-off-by: Neil Armstrong Reviewed-by: Mattijs Korpershoek --- drivers/usb/dwc3/io.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/io.h b/drivers/usb/dwc3/io.h index 04791d4c9be..1aaf5413c6d 100644 --- a/drivers/usb/dwc3/io.h +++ b/drivers/usb/dwc3/io.h @@ -50,6 +50,9 @@ static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value) static inline void dwc3_flush_cache(uintptr_t addr, int length) { - flush_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE)); + uintptr_t start_addr = (uintptr_t)addr & ~(ARCH_DMA_MINALIGN - 1); + uintptr_t end_addr = ALIGN((uintptr_t)addr + length, ARCH_DMA_MINALIGN); + + flush_dcache_range(start_addr, end_addr); } #endif /* __DRIVERS_USB_DWC3_IO_H */