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Fri, 19 Jul 2024 04:00:16 -0700 (PDT) From: Neil Armstrong Date: Fri, 19 Jul 2024 13:00:11 +0200 Subject: [PATCH 2/4] ufs: fix dcache flush and invalidate range calculation MIME-Version: 1.0 Message-Id: <20240719-u-boot-ufs-dcache-fixup-v1-2-b044fc9564e9@linaro.org> References: <20240719-u-boot-ufs-dcache-fixup-v1-0-b044fc9564e9@linaro.org> In-Reply-To: <20240719-u-boot-ufs-dcache-fixup-v1-0-b044fc9564e9@linaro.org> To: Bhupesh Sharma , Neha Malcom Francis , Tom Rini Cc: Marek Vasut , Caleb Connolly , u-boot-qcom@groups.io, u-boot@lists.denx.de, Neil Armstrong X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1874; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=T3zjfDg6dn9NdCFWLjfaWxgHWLxiPmqgJ07RdmwZ1jQ=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBmmkc8202QuuxYoJF3juURPrQYc9nlrAJYN+V3KgJX Y4UhS1WJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZppHPAAKCRB33NvayMhJ0TKBEA CMFgvIjhMQ62QGtSBua2/xHYQE4xHSofUTGX0HhV7XPkVV9iHbnjTERRqvx4dYENp3FP2lP6Vtkx2x gOpSVBWLh+e0yfWLP6bP510tc/MrWPmk+XpBP/p6mWnCKnOVtldxrjRoWbWZYWI+QjYDVFdnoUD26/ V+/16QbJbS0mNLRORpe/5zCM5oAOzo6CXYxEJBi13xJRNTStTYURs3+RrbucDn9FBdhl+2huDhVhj/ sR2g06qj0IBWYKsMDHzSBhMFO5r5XFoEu2Q/VH1KCgV5MmxYo7xkr2375yaDfE750ox+frFe8jvYq5 0vAH8Suw01YLRBrRCZ9/IC9Kh3yNXEwhZVKaBdSC+DgOvVxiocLOBpJ5YAFt2rkg27RpSs/TChVIWu 72OJMV3pAkc1x9RSVCZpxwFgPw/K/Cg/GhHHf1rOasbVMWvqPlRywgUHWMztMCD0B6aru1UydeCLP8 DZRktPeVuYQmZdE8lNYKoriurufK1X3TRBw1a6idC2SnSRhnmVs6dy3vI4yFBciMDMn4BbjwZGIoLz W0Df/EKXlJdNgIxradjDVwhQE2kVqQOwkq83NXlV8zwIE96Etf289dI6usyFn3njJ2QKhIPHx24i6I nhd0bpLvsNAPJa3FXDuBftQMMQ+RlfaQXeXGKof73sFluym69C1iPxgFCx+A== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The current calculation will omit doing a flush/invalidate on the last cacheline if the base address is not aligned with DMA_MINALIGN. This causes commands failures and write corruptions on Qualcomm platforms. Signed-off-by: Neil Armstrong --- drivers/ufs/ufs.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c index bc86903245c..db487d1ff9a 100644 --- a/drivers/ufs/ufs.c +++ b/drivers/ufs/ufs.c @@ -704,11 +704,11 @@ static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba) */ static void ufshcd_cache_flush_and_invalidate(void *addr, unsigned long size) { - uintptr_t aaddr = (uintptr_t)addr & ~(ARCH_DMA_MINALIGN - 1); - unsigned long asize = ALIGN(size, ARCH_DMA_MINALIGN); + uintptr_t start_addr = (uintptr_t)addr & ~(ARCH_DMA_MINALIGN - 1); + uintptr_t end_addr = ALIGN((uintptr_t)addr + size, ARCH_DMA_MINALIGN); - flush_dcache_range(aaddr, aaddr + asize); - invalidate_dcache_range(aaddr, aaddr + asize); + flush_dcache_range(start_addr, end_addr); + invalidate_dcache_range(start_addr, end_addr); } /** @@ -1467,13 +1467,13 @@ static void prepare_prdt_table(struct ufs_hba *hba, struct scsi_cmd *pccb) } if (pccb->dma_dir == DMA_TO_DEVICE) { /* Write to device */ - flush_dcache_range(aaddr, aaddr + - ALIGN(datalen, ARCH_DMA_MINALIGN)); + flush_dcache_range(aaddr, + ALIGN((uintptr_t)pccb->pdata + datalen, ARCH_DMA_MINALIGN)); } /* In any case, invalidate cache to avoid stale data in it. */ - invalidate_dcache_range(aaddr, aaddr + - ALIGN(datalen, ARCH_DMA_MINALIGN)); + invalidate_dcache_range(aaddr, + ALIGN((uintptr_t)pccb->pdata + datalen, ARCH_DMA_MINALIGN)); table_length = DIV_ROUND_UP(pccb->datalen, MAX_PRDT_ENTRY); buf = pccb->pdata;