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Wed, 24 Jul 2024 08:48:17 -0700 (PDT) From: Neil Armstrong Date: Wed, 24 Jul 2024 17:48:10 +0200 Subject: [PATCH v2 2/3] usb: dwc3: fix dcache flush range calculation MIME-Version: 1.0 Message-Id: <20240724-u-boot-dwc3-gadget-dcache-fixup-v2-2-65836d699a71@linaro.org> References: <20240724-u-boot-dwc3-gadget-dcache-fixup-v2-0-65836d699a71@linaro.org> In-Reply-To: <20240724-u-boot-dwc3-gadget-dcache-fixup-v2-0-65836d699a71@linaro.org> To: Marek Vasut , Tom Rini , Lukasz Majewski , Mattijs Korpershoek Cc: Caleb Connolly , u-boot-qcom@groups.io, u-boot@lists.denx.de, Neil Armstrong X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1172; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=srY3udycfvqYMAFtZZ11qUpBrqT3tgodDPaWL7DnMTs=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBmoSI8fsFRKV70il9VEJqdZNr1wcJolgjcgpszJhKZ +OXeJhaJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZqEiPAAKCRB33NvayMhJ0Vt0D/ 0eq6hnxu9FDrX1Y1nlW0a0Z0k2e6o24IWb9IwzyNBoTQATaQGd6rIVn8oYQne7AndiTJP2qi3pmVyW 1a5hrwHXQ9tcS2vcw5xibG/NZEfNKtN/7pycBhMRgAPScpEdffDNcPN+AWaXZ10ose3gXy489HXN4m JDQK2K3c+Ku77XcbO3yjXaibxux0Qs/o0Kc3nwMAI43bFD9HT8uW84rgfrcVeFx/4mAc9trC1lcXk1 nHfooUQ0uZxF4//I9BccyK+V023LBwB5sXY2XXznjGS92Tm/wtGiCyLiwp/n5xER7nvHkLUJ72r833 4U4EuDRoanRkUDpQqxcBh9UCPod4rd2uSzteobjh9JdUl0S3vS86WPB9b0I4i1/Kijo5qezZlmOGKw memsoQcPaRFycidZaXp81uusNbiOV3IaepqGUbxBVI9pustDD3w5o+ec5qvJ0SRw1DsNBzyC96MQUQ OvMWK7xtL7JR6/Y1jvyhcREt6SF4X+5Ec7WCrxgJBwYnQnu28My3Qo5ppfgFKfqcyOokHnA17IfNB2 615gouZaRf0AhpQG12+Fjh2pWd0K8RZI/idx6xAocUu+9Fi0QozZCMvUNPQj+8AYxuL32cmi2epIKw VQs/iCoSxXvkZ4AR1Jo7LR7uF4L68XZRurkJyVi+mAMsDnylNsg/CpsqW9MA== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The current flush operation will omit doing a flush/invalidate on the first and last bytes if the base address and size are not aligned with DMA_MINALIGN. This causes operation failures Qualcomm platforms. Take in account the alignment and size of the buffer and also flush the previous and last cacheline. Reviewed-by: Mattijs Korpershoek Signed-off-by: Neil Armstrong --- drivers/usb/dwc3/io.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/io.h b/drivers/usb/dwc3/io.h index 04791d4c9be..1aaf5413c6d 100644 --- a/drivers/usb/dwc3/io.h +++ b/drivers/usb/dwc3/io.h @@ -50,6 +50,9 @@ static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value) static inline void dwc3_flush_cache(uintptr_t addr, int length) { - flush_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE)); + uintptr_t start_addr = (uintptr_t)addr & ~(ARCH_DMA_MINALIGN - 1); + uintptr_t end_addr = ALIGN((uintptr_t)addr + length, ARCH_DMA_MINALIGN); + + flush_dcache_range(start_addr, end_addr); } #endif /* __DRIVERS_USB_DWC3_IO_H */