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Fri, 11 Oct 2024 07:38:29 -0700 (PDT) From: Neil Armstrong Date: Fri, 11 Oct 2024 16:38:25 +0200 Subject: [PATCH v4 2/3] usb: dwc3: fix dcache flush range calculation MIME-Version: 1.0 Message-Id: <20241011-u-boot-dwc3-gadget-dcache-fixup-v4-2-5f3498d8035b@linaro.org> References: <20241011-u-boot-dwc3-gadget-dcache-fixup-v4-0-5f3498d8035b@linaro.org> In-Reply-To: <20241011-u-boot-dwc3-gadget-dcache-fixup-v4-0-5f3498d8035b@linaro.org> To: Marek Vasut , Tom Rini , Lukasz Majewski , Mattijs Korpershoek , Bin Meng Cc: Caleb Connolly , u-boot-qcom@groups.io, u-boot@lists.denx.de, Neil Armstrong X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1198; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=WkL4d/oa8d34YakzfvLf/4CbUT+vDaGFbb8LMUkM3jI=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnCThi0vfvCHEtS6Gjwjl8xdTIqFbvrejcM/MdhEED EWMjkQ6JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZwk4YgAKCRB33NvayMhJ0UcaD/ 9xoXjoqiL1MSRbexPpqp1EWMOQjIma1e20FtYPrhz5SjSbqreZASFd4euKGunE98+j6FEipIwcY6Na 2X7K5EpsJkXK216i74PqJTcfGX9+7PgWBHkPEAx/kWdJRjbHOvupQqDrFpT9We1ODsXQ5dHLZzg0GM aqF7dQ0Zm21Oy06Yo3hRYZzvsWMcmXHXLHD3PFD8GJ6o4ihdDxgkjDhcfvFIlr9HgNgcnrPrvaw/Dv mnJXmjGbCwzXMEtE2ml30a7CTPUzkHa40a+OOCtt7Y7TuA1fSGc4AD5BWUI2lrK8zrTR9fp3BPpE+W xUNUkujWUTfav7w4w+u3KalVsReCp37l9zfW1J6ovvtlvowYGBXjZwNjBzVvsJmhijzxITkGAzfiZz qWApgqWLAhj54Xsv7yDMQi/uFf4k8NA/x3y2G04egHbpqY3QNc4Bdz6ysxXaD9OZyQgxTVLjt7fj0V jv7+WDjJs1PJDgouLZE8gLHs0HGCenI5XhSC/9Uene31VMsI1PE7hLTzR3qrBx4WOJnWoV5n2pjNg+ EiVfv0OcPcvNfVELcECo4YtTK5CkrvmrR0SzFvXs2/2E6B0295cQrJJ7CknrN/ILn36MWXNTqa5KGs Vnt0R51xbqZMOHEY/e7dVVCDGItIusexMLyYP8TE7frTZKQGOMB4j4U4gOog== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The current flush operation will omit doing a flush/invalidate on the first and last bytes if the base address and size are not aligned with CACHELINE_SIZE. This causes operation failures Qualcomm platforms. Take in account the alignment and size of the buffer and also flush the previous and last cacheline. Reviewed-by: Mattijs Korpershoek Signed-off-by: Neil Armstrong Reviewed-by: Marek Vasut --- drivers/usb/dwc3/io.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/io.h b/drivers/usb/dwc3/io.h index 04791d4c9be..0ede323671b 100644 --- a/drivers/usb/dwc3/io.h +++ b/drivers/usb/dwc3/io.h @@ -50,6 +50,9 @@ static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value) static inline void dwc3_flush_cache(uintptr_t addr, int length) { - flush_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE)); + uintptr_t start_addr = (uintptr_t)addr & ~(CACHELINE_SIZE - 1); + uintptr_t end_addr = ALIGN((uintptr_t)addr + length, CACHELINE_SIZE); + + flush_dcache_range((unsigned long)start_addr, (unsigned long)end_addr); } #endif /* __DRIVERS_USB_DWC3_IO_H */