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Mon, 25 Nov 2024 00:34:30 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825f98b3a4sm10013421f8f.0.2024.11.25.00.34.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Nov 2024 00:34:30 -0800 (PST) From: Neil Armstrong Date: Mon, 25 Nov 2024 09:34:26 +0100 Subject: [PATCH 1/4] clk: qcom: add clk_phy_mux_enable() for PCIe PIPE clock MIME-Version: 1.0 Message-Id: <20241125-topic-pcie-clk-v1-1-4315d1e4e164@linaro.org> References: <20241125-topic-pcie-clk-v1-0-4315d1e4e164@linaro.org> In-Reply-To: <20241125-topic-pcie-clk-v1-0-4315d1e4e164@linaro.org> To: Lukasz Majewski , Sean Anderson , Caleb Connolly , Sumit Garg , Tom Rini Cc: u-boot-qcom@groups.io, u-boot@lists.denx.de, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2239; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=g0FjaoqpfjI6frI33mzwzYPVRURIl7UqnNT+yHjBoio=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnRDaT+K3wVPO02SpP+t0Pd6n+o9pk7xcXINgm2VIl 7tXrAtSJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ0Q2kwAKCRB33NvayMhJ0XTqD/ 45IA0o/uj35dAGlA3Jn6F2kdMMIZYReGVQX9r1hs/wo2Z4CHLQ5wIinhQ4rzE01FVZNzrFTF4TnqBO MUaOhVePDzrElio2aWBxKAlnYHb+xkTHlqVI1S7wCni7fGL/yFQKQwGCc+c5gn4twTQ1CelyqiA+Dl P3rzJnp6Cg505FL4nmTBTWPTbM0e+LXuyuzhDEtjCdmuan+1io8FV1m/oNtf8uwmT5ahicLPQwHkJB D/1fl7qKYwuyZ8ZGh/6DZLZA9AOzUjHlvdwOf8o8y57lCSSDF5YJU3RIAPiem2w5+hPjKcpUPToVqj k35RBf0LLeiTiRSw1aqhI9TbJ2qCKo84N+766t2mzdSMvxLAz5ZF2cHdk6inIdZe8QCBXJ/9EEXBzi ezhaWB1xqD75kbsNyOrhDV/JDnHcRSeccbL/vu6aQ7uyZVB+v693IHe/jod/5zgpd+61yFaWtnsLUf C9gR1pXVk66mXUK4kNWJkihh3DliPBJ5icaK0GnKZQK09q4OE2Lg1ApJtNkaDEe1f6BrOk6Z86sPA5 1FcZFlXCYavDGjL9zWagSNSdWjQrprGZfRX6thpv/cBG9g+tjSLLnnciP7HwzCFXQ8cciEyAZYADs3 ssnLyYj/v5m6PPswy3YjOfld6ieb+C7MmP5ljIoctWLZCLeqbYGI7x31GW/A== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The PCIe PIPE clock requires a special setup function to mux & enable the clock from the PCIe PHY before the PHY has enabled the clock. Import the clk_phy_mux_enable() from the Linux driver to use the same implementation regarding the PIPE clock. Signed-off-by: Neil Armstrong --- drivers/clk/qcom/clock-qcom.c | 19 +++++++++++++++++++ drivers/clk/qcom/clock-qcom.h | 2 ++ 2 files changed, 21 insertions(+) diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index 25ca67e537d112dda236837d3d3984f9b666365e..7687bbe6a23b436e4ddf3b29d1c910062961126d 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -166,6 +166,25 @@ void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div, clk_bcr_update(base + cmd_rcgr); } +#define PHY_MUX_MASK GENMASK(1, 0) +#define PHY_MUX_PHY_SRC 0 +#define PHY_MUX_REF_SRC 2 + +void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled) +{ + u32 cfg; + + /* setup src select and divider */ + cfg = readl(base + cmd_rcgr); + cfg &= ~(PHY_MUX_MASK); + if (enabled) + cfg |= FIELD_PREP(PHY_MUX_MASK, PHY_MUX_PHY_SRC); + else + cfg |= FIELD_PREP(PHY_MUX_MASK, PHY_MUX_REF_SRC); + + writel(cfg, base + cmd_rcgr); +} + const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate) { if (!f) diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h index 78d9b1d81ece1b3dd96b7bd0ab1a69fa016523b6..ff336dea39cf5cbe35f37f93669285897ba185a4 100644 --- a/drivers/clk/qcom/clock-qcom.h +++ b/drivers/clk/qcom/clock-qcom.h @@ -6,6 +6,7 @@ #define _CLOCK_QCOM_H #include +#include #define CFG_CLK_SRC_CXO (0 << 8) #define CFG_CLK_SRC_GPLL0 (1 << 8) @@ -102,6 +103,7 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr, int div, int m, int n, int source, u8 mnd_width); void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div, int source); +void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled); static inline void qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id) {