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Mon, 25 Nov 2024 00:34:31 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825f98b3a4sm10013421f8f.0.2024.11.25.00.34.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Nov 2024 00:34:30 -0800 (PST) From: Neil Armstrong Date: Mon, 25 Nov 2024 09:34:27 +0100 Subject: [PATCH 2/4] clk: qcom: sm8550: add support for PCIe clocks MIME-Version: 1.0 Message-Id: <20241125-topic-pcie-clk-v1-2-4315d1e4e164@linaro.org> References: <20241125-topic-pcie-clk-v1-0-4315d1e4e164@linaro.org> In-Reply-To: <20241125-topic-pcie-clk-v1-0-4315d1e4e164@linaro.org> To: Lukasz Majewski , Sean Anderson , Caleb Connolly , Sumit Garg , Tom Rini Cc: u-boot-qcom@groups.io, u-boot@lists.denx.de, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2499; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=7v8yHf1Xr5hvCGhLH17xt8vT38yWqbNI8HP3CAE9U9s=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnRDaT79p41vv0Q7UbtpW/HMcQHMSnX+rk+SWMwYoH 4Brfb8+JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ0Q2kwAKCRB33NvayMhJ0U87D/ 0Vwm1pLfmG8Rs9lQ+eat4NAA3FC9TeRMEfWn5K4tBKW0P4wSYKhzj1AG6WmGVoZf0ri6YC04+bO195 PTJtzNljmwfFhiIy6T8tThGF6K1InLS82Xmnip8yzMJZpb37c4s9z/CBHVtheG+iSGjmZbExSVSdZP KCXXJrgbBo5QStnLiqXvfDehquJ33iDSnBTZu5TjMeGsPTW+d+C87pqOIxAe/DiPerPOhNHOGPnq92 RKfXkay5oNdU7OFDBW8tMkC9LwFT3ZyvpEgsoZQaR7uErrlETRfcIluZJZy6TmZ2pGUj4jOyzDtGEf EbMrzyrBJ6ZiEDY5J4zno0BiCpbO3fl6Eoa2c6vGAfjZyqMg+PZjamVi5kHD/Onn4Zv4XEf2GB69r1 EmKxcrcLWiCS6VQrxuno+zmCPdyWrwWuFQ/JKs45kQbP5lZmT0Z6PGJaet9pC5x8s08SGw7GRfi2Ku e0JYvqxrbkZHobJl9pSbzEYiVGbfu4qkDZo3bJ6Sqj5d5ighxbG09J+YI86CymkjPZcB+pW0fceI22 SuXxeUrRu3MBAoqjBquaSOKsAzfmDXoNlrf2h1SGgZYgS9BausvUZqUrAPKp+Jm62LlV5bzEXZiD1i IBKy1Nmtdz8Whvq4S09GqNnGWzynC8YxAMhYqR/xtwnroV+TYNanHecX67Ww== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add the PCIe clocks for the SM8550 GCC. Signed-off-by: Neil Armstrong --- drivers/clk/qcom/clock-sm8550.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/clk/qcom/clock-sm8550.c b/drivers/clk/qcom/clock-sm8550.c index c0249925cc7eb165faefea35ef29c5ff59faf07f..62b5a409e8e08243ad53a0bc58af1c7754a3d950 100644 --- a/drivers/clk/qcom/clock-sm8550.c +++ b/drivers/clk/qcom/clock-sm8550.c @@ -57,6 +57,16 @@ static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { { } }; +static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { + F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0), + { } +}; + static ulong sm8550_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -84,6 +94,24 @@ static ulong sm8550_set_rate(struct clk *clk, ulong rate) case GCC_USB3_PRIM_PHY_AUX_CLK_SRC: clk_rcg_set_rate(priv->base, 0x39070, 0, 0); return TCXO_DIV2_RATE; + case GCC_PCIE_0_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x6b074, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_PCIE_1_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x8d07c, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_PCIE_0_PHY_RCHNG_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate); + clk_rcg_set_rate(priv->base, 0x6b058, freq->pre_div, freq->src); + return freq->freq; + case GCC_PCIE_1_PHY_RCHNG_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate); + clk_rcg_set_rate(priv->base, 0x8d060, freq->pre_div, freq->src); + return freq->freq; default: return 0; } @@ -182,6 +210,14 @@ static int sm8550_enable(struct clk *clk) qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK); qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); break; + case GCC_PCIE_0_PIPE_CLK: + // GCC_PCIE_0_PIPE_CLK_SRC + clk_phy_mux_enable(priv->base, 0x6b070, true); + break; + case GCC_PCIE_1_PIPE_CLK: + // GCC_PCIE_1_PIPE_CLK_SRC + clk_phy_mux_enable(priv->base, 0x8d078, true); + break; } qcom_gate_clk_en(priv, clk->id);