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Mon, 25 Nov 2024 00:34:32 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825f98b3a4sm10013421f8f.0.2024.11.25.00.34.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Nov 2024 00:34:31 -0800 (PST) From: Neil Armstrong Date: Mon, 25 Nov 2024 09:34:28 +0100 Subject: [PATCH 3/4] clk: qcom: sm8650: add support for PCIe clocks MIME-Version: 1.0 Message-Id: <20241125-topic-pcie-clk-v1-3-4315d1e4e164@linaro.org> References: <20241125-topic-pcie-clk-v1-0-4315d1e4e164@linaro.org> In-Reply-To: <20241125-topic-pcie-clk-v1-0-4315d1e4e164@linaro.org> To: Lukasz Majewski , Sean Anderson , Caleb Connolly , Sumit Garg , Tom Rini Cc: u-boot-qcom@groups.io, u-boot@lists.denx.de, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2499; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=Bdz2SeZUb5BmZho1bLFOZ+RD51DphnJ1Z9qxkJ4pego=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnRDaUCjLpP9/ummMwNfnKEJorMPql122ewa75t2JU 7MHp9kyJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ0Q2lAAKCRB33NvayMhJ0aeVD/ 4yCAhRkY5XhYUIRbLZ/U6rGGSlitKGScU23jULlxXmwUPJ+SNsHNoiExJiT0VePwV0Tqa6jmlAvJxD CdWZZDCfpOiWvQu8IgvZffc0yaeDyhAdlmhumS5Zb0mYHsXvYez3o6KICIa8TrWNubT/SRHaHsWKLm SXOBNSISQSvth6x8SmmWJK1/m0oOFLC5LQc+D3rcvcI+U8y+ESYd5qcBWd7iBoCiojN5Mqcd1Zc56v UcFYjjiW0r88XB3CQxbyO95xKzDEFZjnsvYdXWI+c08sq5oYwd1fwtPyfIoK9mNZZj+oPejjdPtB7W 2hK29LNf+Vb6Epnj/t3ieuVoR2XqdQ86MlK9fl3aGv7Bunt4QXWYbi3nzH2TmP/0kAN6ty5bPtWDgk CJ4ooleLRPbjYBx0eOgq7Rs4XSTC0oMJACD++ZI4dOep9L181MrbsXUlaPOxcePfHCW+zSmPt+KmWZ hU7YjlncocuxDiWANMF3y57ScVyLdtXJoLBQHRqG/fTW4f4m82B9mC17QpQ1DtJcMSYyKfxLxonhm2 vHgdN4M14VyGZ3Z24KDC3hOwqvFdjWvTyDNixRUgJFlSFc/iLb7zyo6S/Ag7G5QRJEPKk+lTTM3v2C A2wLgXkpdSltDOX2AFi9HuH3VSbwPcnhwZj5PAtY5uK4NpzawbUmTdow9mpg== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add the PCIe clocks for the SM8650 GCC. Signed-off-by: Neil Armstrong --- drivers/clk/qcom/clock-sm8650.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/clk/qcom/clock-sm8650.c b/drivers/clk/qcom/clock-sm8650.c index 0ce83e9b24375820016397c3c5491dd9d44edb4b..9baaecb571f6c575c0e7c48d66214c1331b6642f 100644 --- a/drivers/clk/qcom/clock-sm8650.c +++ b/drivers/clk/qcom/clock-sm8650.c @@ -54,6 +54,16 @@ static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { { } }; +static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { + F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0), + { } +}; + static ulong sm8650_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -81,6 +91,24 @@ static ulong sm8650_set_rate(struct clk *clk, ulong rate) case GCC_USB3_PRIM_PHY_AUX_CLK_SRC: clk_rcg_set_rate(priv->base, 0x39070, 0, 0); return TCXO_DIV2_RATE; + case GCC_PCIE_0_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x6b074, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_PCIE_1_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x8d07c, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_PCIE_0_PHY_RCHNG_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate); + clk_rcg_set_rate(priv->base, 0x6b058, freq->pre_div, freq->src); + return freq->freq; + case GCC_PCIE_1_PHY_RCHNG_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate); + clk_rcg_set_rate(priv->base, 0x8d060, freq->pre_div, freq->src); + return freq->freq; default: return 0; } @@ -179,6 +207,14 @@ static int sm8650_enable(struct clk *clk) qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK); qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); break; + case GCC_PCIE_0_PIPE_CLK: + // GCC_PCIE_0_PIPE_CLK_SRC + clk_phy_mux_enable(priv->base, 0x6b070, true); + break; + case GCC_PCIE_1_PIPE_CLK: + // GCC_PCIE_1_PIPE_CLK_SRC + clk_phy_mux_enable(priv->base, 0x8d078, true); + break; } qcom_gate_clk_en(priv, clk->id);