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[176.92.191.135]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43987088ecbsm111659865e9.31.2025.02.20.05.55.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Feb 2025 05:55:56 -0800 (PST) From: Ilias Apalodimas To: xypron.glpk@gmx.de, mark.kettenis@xs4all.nl Cc: Ilias Apalodimas , Alexey Brodkin , Eugeniy Paltsev , Tom Rini , Caleb Connolly , Neil Armstrong , Sumit Garg , Huan Wang , Angelo Dureghello , Thomas Chou , Rick Chen , Leo , Marek Vasut , Nobuhiro Iwamatsu , Max Filippov , Sughosh Ganu , Simon Glass , Jerome Forissier , Sam Protsenko , =?utf-8?q?Pierre-Cl=C3=A9ment_T?= =?utf-8?q?osi?= , Peng Fan , Richard Henderson , Sam Edwards , Peter Hoyes , Andre Przywara , Patrick Rudolph , Sam Day , Mayuresh Chitale , Mattijs Korpershoek , Stefan Roese , Alex Shumsky , Joshua Watt , Jagan Teki , Jiaxun Yang , Evgeny Bachinin , Michal Simek , Christian Marangi , Jonas Jelonek , uboot-snps-arc@synopsys.com, u-boot@lists.denx.de, u-boot-qcom@groups.io Subject: [PATCH v2 4/6] arm64: mmu_change_region_attr() add an option not to break PTEs Date: Thu, 20 Feb 2025 15:54:41 +0200 Message-ID: <20250220135506.151894-5-ilias.apalodimas@linaro.org> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250220135506.151894-1-ilias.apalodimas@linaro.org> References: <20250220135506.151894-1-ilias.apalodimas@linaro.org> MIME-Version: 1.0 X-Mailman-Approved-At: Thu, 20 Feb 2025 22:01:46 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The ARM ARM on section 8.17.1 describes the cases where break-before-make is required when changing live page tables. Since we can use this function to tweak block and page permssions, where BBM is not required add an extra argument to the function. While at it add a function description. Signed-off-by: Ilias Apalodimas --- arch/arm/cpu/armv8/cache_v8.c | 6 +++++- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 10 +++++----- arch/arm/include/asm/system.h | 11 ++++++++++- arch/arm/mach-snapdragon/board.c | 2 +- 4 files changed, 21 insertions(+), 8 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index c4b3da4a8da7..670379e17b7a 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -972,11 +972,14 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, * The procecess is break-before-make. The target region will be marked as * invalid during the process of changing. */ -void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs) +void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs, bool bbm) { int level; u64 r, size, start; + if (!bbm) + goto skip_break; + start = addr; size = siz; /* @@ -1001,6 +1004,7 @@ void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs) gd->arch.tlb_addr + gd->arch.tlb_size); __asm_invalidate_tlb_all(); +skip_break: /* * Loop through the address range until we find a page granule that fits * our alignment constraints, then set it to the new cache attributes diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index d2d3e346a36f..caf1dab05936 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1573,7 +1573,7 @@ void update_early_mmu_table(void) PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | - PTE_TYPE_VALID); + PTE_TYPE_VALID, true); } else { mmu_change_region_attr( CFG_SYS_SDRAM_BASE, @@ -1581,7 +1581,7 @@ void update_early_mmu_table(void) PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | - PTE_TYPE_VALID); + PTE_TYPE_VALID, true); #ifdef CONFIG_SYS_DDR_BLOCK3_BASE #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE" @@ -1594,7 +1594,7 @@ void update_early_mmu_table(void) PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | - PTE_TYPE_VALID); + PTE_TYPE_VALID, true); mmu_change_region_attr( CONFIG_SYS_DDR_BLOCK3_BASE, gd->ram_size - @@ -1603,7 +1603,7 @@ void update_early_mmu_table(void) PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | - PTE_TYPE_VALID); + PTE_TYPE_VALID, true); } else #endif { @@ -1614,7 +1614,7 @@ void update_early_mmu_table(void) PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | - PTE_TYPE_VALID); + PTE_TYPE_VALID, true); } } } diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 091082281c73..08e6e52cc673 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -303,7 +303,16 @@ void flush_l3_cache(void); * @emerg: Also map the region in the emergency table */ void mmu_map_region(phys_addr_t start, u64 size, bool emerg); -void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs); + +/** + * mmu_change_region_attr() - change a mapped region attributes + * + * @start: Start address of the region + * @size: Size of the region + * @aatrs: New attributes + * @bbm: Perform a break-before-make on the page tables entries + */ +void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs, bool bbm); /* * smc_call() - issue a secure monitor call diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index 2ef936aab757..13f4e8e640ef 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -577,7 +577,7 @@ static void carve_out_reserved_memory(void) if (i == count || start + size < res[i].start - SZ_2M) { debug(" 0x%016llx - 0x%016llx: reserved\n", start, start + size); - mmu_change_region_attr(start, size, PTE_TYPE_FAULT); + mmu_change_region_attr(start, size, PTE_TYPE_FAULT, true); /* If this is the final region then quit here before we index * out of bounds... */