From patchwork Tue Feb 18 12:20:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 236494 List-Id: U-Boot discussion From: michal.simek at xilinx.com (Michal Simek) Date: Tue, 18 Feb 2020 13:20:40 +0100 Subject: [PATCH 10/16] arm64: dts: zynqmp: Add clk cells for sdhci In-Reply-To: References: Message-ID: <7d6a2e07589348942ebeec0359a2513f38374d67.1582028304.git.michal.simek@xilinx.com> From: Ashok Reddy Soma Add clock-cells and clock-output-names for sdhci0 and sdhci1. These are needed for linux sdhci driver from 5.4 version onwards. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index ed28f1f695bb..b117fc43c6d2 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -791,6 +791,8 @@ power-domains = <&zynqmp_firmware PD_SD_0>; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; + #clock-cells = <1>; + clock-output-names = "clk_out_sd0", "clk_in_sd0"; }; sdhci1: mmc at ff170000 { @@ -807,6 +809,8 @@ power-domains = <&zynqmp_firmware PD_SD_1>; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; + #clock-cells = <1>; + clock-output-names = "clk_out_sd1", "clk_in_sd1"; }; pinctrl0: pinctrl at ff180000 {