From patchwork Mon May  4 15:18:42 2020
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X-Patchwork-Submitter: Fabio Estevam <festevam@gmail.com>
X-Patchwork-Id: 245038
List-Id: U-Boot discussion <u-boot.lists.denx.de>
From: festevam at gmail.com (Fabio Estevam)
Date: Mon, 4 May 2020 12:18:42 -0300
Subject: [PATCH 6/8] ARM: imx8m: Fix reset in SPL on NXP iMX8MP EVK
In-Reply-To: <7b859a29ab32e4de8b1f37a6da0f1b59b06e813d.camel@denx.de>
References: <20200429130428.124788-1-hws@denx.de>
 <20200429130428.124788-7-hws@denx.de>
 <CAOMZO5BH6m6Rt4fb=JS4s1duLDmT=U0DscCbDOiCKxmmwESC7Q@mail.gmail.com>
 <ad38e38c-f5f8-cae5-1b56-b19d424f1222@denx.de>
 <7b859a29ab32e4de8b1f37a6da0f1b59b06e813d.camel@denx.de>
Message-ID: <CAOMZO5DBZ19vn2fytk37eTcZOgV+m61DUMJPuc7W+rP=Y5fU4Q@mail.gmail.com>

On Mon, May 4, 2020 at 12:05 PM Harald Seiler <hws at denx.de> wrote:

> "Failed to find clock node. Check device tree" comes from spl_board_init()
> in board/freescale/imx8mp_evk/spl.c; line 56:
>
>         ret = uclass_get_device_by_name(UCLASS_CLK,
>                                         "clock-controller at 30380000",
>                                         &dev);
>
> I see that wdog1 references the same clock here:
>
> arch/arm/dts/imx8mp.dtsi; line 222:
>
>         wdog1: watchdog at 30280000 {
>                 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
>                 reg = <0x30280000 0x10000>;
>                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
>                 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
>                 status = "disabled";
>         };
>
> So the two issues are very likely related.  The relevant clock's node is
> also enabled for SPL so I think the driver might be missing here.  Maybe
> you need to add
>
>     CONFIG_SPL_CLK_IMX8MP=y
>
> to your defconfig?

I tried like this:


but still only prints:

U-Boot SPL 2020.07-rc1-00014-g8142a97d54-dirty (May 04 2020 - 12:16:25 -0300)

--- a/configs/imx8mp_evk_defconfig
+++ b/configs/imx8mp_evk_defconfig
@@ -57,7 +57,9 @@ CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_SPL_DM=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
 CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MP=y
 CONFIG_CLK_IMX8MP=y
 CONFIG_MXC_GPIO=y
 CONFIG_DM_PCA953X=y